13

INA220

www.ti.com

SBOS459E – JUNE 2009 – REVISED JANUARY 2016

Product Folder Links: INA220

Submit Documentation Feedback

Copyright © 2009–2016, Texas Instruments Incorporated

Programming (continued)

To address a specific device, the master initiates a START condition by pulling the data signal line (SDA) from a

high to a low logic level while SCL is high. All slaves on the bus shift in the slave address byte on the rising edge

of SCL, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the

slave being addressed responds to the master by generating an Acknowledge and pulling SDA low.

Data transfer is then initiated and eight bits of data are sent, followed by an Acknowledge bit. During data

transfer, SDA must remain stable while SCL is high. Any change in SDA while SCL is high is interpreted as a

START or STOP condition.

After all data have been transferred, the master generates a STOP condition, indicated by pulling SDA from low

to high while SCL is high. The INA220 includes a 28-ms timeout on its interface to prevent locking up an SMBus.

8.5.4.1 Serial Bus Address

To communicate with the INA220, the master must first address slave devices through a slave address byte. The

slave address byte consists of seven address bits, and a direction bit indicating the intent of executing a read or

write operation.

The INA220 has two address pins, A0 and A1. Table 1 describes the pin logic levels for each of the 16 possible

addresses. The state of pins A0 and A1 is sampled on every bus communication and should be set before any

activity on the interface occurs. The address pins are read at the start of each communication event.

Table 1. INA220 Address Pins and Slave Addresses

A1

A0

SLAVE ADDRESS

GND

GND

1000000

GND

1000001

GND

SDA

1000010

GND

SCL

1000011

GND

1000100

1000101

SDA

1000110

SCL

1000111

SDA

GND

1001000

SDA

1001001

SDA

SDA

1001010

SDA

SCL

1001011

SCL

GND

1001100

SCL

1001101

SCL

SDA

1001110

SCL

SCL

1001111

8.5.4.2 Serial Interface

open-drain I/O lines SDA and SCL. The SDA and SCL pins feature integrated spike suppression filters and

Schmitt triggers to minimize the effects of input spikes and bus noise. The INA220 supports the transmission

protocol for fast (1-kHz to 400-kHz) and high-speed (1-kHz to 2.56-MHz) modes. All data bytes are transmitted

most significant byte first.

8.5.5 Writing to and Reading from the INA220

Accessing a particular register on the INA220 is accomplished by writing the appropriate value to the register

pointer. Refer to Table 2 for a complete list of registers and corresponding addresses. The value for the register

pointer, as shown in Figure 18, is the first byte transferred after the slave address byte with the R/W bit LOW.

Every write operation to the INA220 requires a value for the register pointer.