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INA220

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SBOS459E – JUNE 2009 – REVISED JANUARY 2016

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Copyright © 2009–2016, Texas Instruments Incorporated

(1)

Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not ensured and not

production tested. Condition: A0=A1=0.

(1)

Type: R = Read only, R/W = Read/Write.

(2)

The Power register and Current register default to 0 because the Calibration register defaults to 0, yielding a zero current value until the

Calibration register is programmed.

8.5.5.1 High-Speed Two-Wire Mode

When the bus is idle, both the SDA and SCL lines are pulled high by the pullup devices. The master generates a

start condition followed by a valid serial byte containing high-speed (HS) master code 00001XXX. This

transmission is made in fast (400 kbps) or standard (100 kbps) (F/S) mode at no more than 400 kbps. The

INA220 does not acknowledge the HS master code, but does recognize it and switches its internal filters to

support 2.56-Mbps operation.

The master then generates a repeated start condition (a repeated start condition has the same timing as the start

condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission

speeds up to 2.56 Mbps are allowed. Instead of using a stop condition, repeated start conditions should be used

to secure the bus in HS-mode. A STOP condition ends the HS-mode and switches all the internal filters of the

INA220 to support the F/S mode. See Bus Timing Diagram Definitions(1) and Figure 1 for timing.

8.5.5.2 Power-Up Conditions

bus General Call Reset.

8.6 Register Maps

8.6.1 Register Information

The INA220 uses a bank of registers for holding configuration settings, measurement results, and status

information. Table 2 summarizes the INA220 registers; Functional Block Diagram illustrates the registers.

Register contents are updated 4

μs after completion of the write command. Therefore, a 4-μs delay is required

between completion of a write to a given register and a subsequent read of that register (without changing the

pointer) when using SCL frequencies in excess of 1 MHz.

Table 2. Summary of Register Set

POINTER

ADDRESS

REGISTER NAME

FUNCTION

POWER-ON RESET

HEX

BINARY

HEX

00

Configuration

All-register reset, settings for bus

voltage range, PGA gain, ADC

resolution/averaging.

00111001 10011111

399F

R/W

01

Shunt voltage

Shunt voltage measurement data.

Shunt voltage

—

R

02

Bus voltage

Bus voltage measurement data.

Bus voltage

—

R

03

Power measurement data.

00000000 00000000

0000

R

04

Contains the value of the current flowing

through the shunt resistor.

00000000 00000000

0000

R

05

Calibration

Sets full-scale range and LSB of current

and power measurements. Overall

system calibration.

00000000 00000000

0000

R/W