Reference

Timing

CLK

OVR

D[13:0]

CLK

6

DRY

VREF

VIN

VIN

TH1

5

5

S

DAC2

ADC2

ADC3

S

DAC1

ADC1

DigitalErrorCorrection

+

–

+

–

DRY

OVR

A1

TH2

A2

A3

TH3

ADS5474

SLAS525C – JULY 2007 – REVISED JANUARY 2016

www.ti.com

7 Detailed Description

7.1 Overview

The ADS5474 device is a 14-bit, 400-MSPS, monolithic pipeline ADC. The bipolar analog core operates from 5-V

and 3.3-V supplies, while the output uses a 3.3-V supply to provide LVDS-compatible outputs. The conversion

process is initiated by the rising edge of the external input clock. At that instant, the differential input signal is

captured by the input track-and-hold (T&H), and the input sample is converted sequentially by a series of lower

resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling

clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results in

a data latency of 3.5 clock cycles, after which the output data are available as a 14-bit parallel word, coded in

offset binary format.

7.2 Functional Block Diagram

7.3 Feature Description

The analog input for the ADS5474 device consists of an analog pseudo-differential buffer followed by a bipolar

transistor T&H. The analog buffer isolates the source driving the input of the ADC from any internal switching and

presents a high impedance that is easy to drive at high input frequencies, compared to an ADC without a

buffered input. The input common-mode is set internally through a 500-

Ω resistor connected from 3.1 V to each

of the inputs (common-mode is approximately 2.4 V on 12-bit and 13-bit members of this family). This

configuration results in a differential input impedance of 1 k

Ω.

18

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