Fin (MHz)

10

20 30

50 70 100

200 300 500

1000 2000

5000

55

57

59

61

63

65

67

69

71

73

75

D001

35 fs

50 fs

100 fs

150 fs

200 fs

2

2

10 log(

)

20 log(

)

O

O

AMP

Filter

FILTEROUT

FILTEROUT

V

V

SNR

E

E

+

=

´

=

´

ADS5474

www.ti.com

SLAS525C – JULY 2007 – REVISED JANUARY 2016

Typical Applications (continued)

where

•

•

•

ENB = the brick-wall equivalent noise bandwidth of the filter

•

VO = the amplifier output signal. (which will be full scale input of the ADC expressed in rms)

(6)

In Equation 6, the parameters of the equation can be seen to be in terms of signal amplitude in the numerator

and amplifier noise in the denominator, or SNR. For the numerator, use the full scale voltage specification of the

ADS5474, or 2.2 V peal to peak differential. Because Equation 6 requires the signal voltage to be in rms, convert

2.2 V p-p to 0.7766 V rms.

The noise specification for the LMH3401 is listed as 3.4 (nV /

√Hz), so we will use this value to integrate the

noise component from DC out to the filter cutoff, using the equivalent brick wall filter of 200 MHz × 1.57, or 314

MHz. 3.4 (nV /

√Hz) × 314 MHz yields 60248 nV, or 60.25 µV.

approximately 82.2 dB.

Taking the SNR of the ADC as 69.2 dB from Figure 45, and SNR of the amplifier and filter as 82.2 dB,

Equation 5 predicts the system SNR to be 68.99 dB. In other words, the SNR of the ADC and the SNR of the

front end combine as the square root of the sum of squares, and since the SNR of the amplifier front end is seen

to be much greater than the SNR of the ADC in this example, the SNR of the ADC dominates Equation 5 and the

system SNR is seen to be nearly the SNR of the ADC itself. We assumed our design requirement to be 69 dB,

and after a clocking solution was chosen and an amplifier/filter solution was chosen we have a predicted SNR of

68.99 dB. If we deem 68.99 dB to not be close enough, or wish to have some margin in the design, then either

improving the clock jitter from 100 fs to 50 fs, or replacing the first order filter with a second order filter would get

the predicted system SNR above the 69-dB design requirement.

8.2.3 Application Curves

Figure 45 shows the SNR of the ADC as a function of clock jitter and input frequency for the ADS5474. This plot

of curves take into account the aperture jitter of the ADC, the number of bits of resolution, and the thermal noise

estimation so that the figure may be used to predict SNR for a given input frequency and external clock jitter.

This figure then may be used to set the jitter requirement for the clocking solution for a given input bandwidth

and given design goal for SNR.

Figure 45. SNR vs Input Frequency and External Clock Jitter

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