[

]

20 log(2

)

Jitter

IN

Jitter

SNR

dBc

f

t

p

= -

´

´

´

_

2

2

2

[

]

20 log (10

)

(10

)

(10

)

20

20

20

ThermalNoise

Jitter

Quantization Noise

ADC

SNR

SNR

SNR

SNR

dBc = -

´

-

+

-

+

-

1.76 (6.02

)

MAX

SNR

N

=

+

´

Clock Buffer

CLKINP

CLKINN

R

T

R

T

0.1 µF

0.1 µF

0.1 µF

ADS5474

www.ti.com

SLAS525C – JULY 2007 – REVISED JANUARY 2016

Typical Applications (continued)

Figure 44. Recommended Differential Clock Driving Circuit

8.2.1 Design Requirements

The ADS5474 requires a fully differential analog input with a full-scale range not to exceed 2.2-V peak to peak

differential, biased to a common mode voltage of 3.1 V. In addition the input circuit must provide proper

transmission line termination (or proper load resistors in an amplifier-based solution) so the input of the

impedance of the ADC analog inputs should be considered as well.

The ADS5474 is capable of a typical SNR of 70.1 dBFS for input frequencies of about 130 MHz, which is well

under the Nyquist limit for this ADC operating at 400 Msps. The amplifier and clocking solution will have a direct

impact on performance in terms of SNR, so the amplifier and clocking solution should be selected such that the

SNR performance of at least 69 dBFS is preserved.

8.2.2 Detailed Design Procedure

The ADS5474 has a max sample rate of 400 MHz and an input bandwidth of approximately 1440 MHz, but an

application involving the first Nyquist zone is being considered, therefore limit the frequency bandwidth here to be

under 200 MHz.

8.2.2.1 Clocking source for ADC5474

The signal to noise ratio of the ADC is limited by three different factors: the quantization noise, the thermal noise,

and the total jitter of the sample clock. Quantization noise is driven by the resolution of the ADC, which is 14 bits

for the ADS5474. Thermal noise is typically not noticeable in high speed pipelined converters such as the

ADS5474, but may be estimated by looking at the signal to noise ratio of the ADC with very low input frequencies

and using Equation 1 to solve for thermal noise. (For this estimation, we will look to the ADS5474 datasheet and

take the specified SNR for the lowest frequency listed. The lowest input frequency listed for the ADS5474 is at 30

MHz, and the SNR at that frequency is 70.3 dB, so we will use 70.3 dB as our SNR limit due to thermal noise.

This is just an approximation, and the lower the input frequency that has an SNR specification the better this

approximation would be.) The thermal noise limits the SNR at low input frequencies while the clock jitter sets the

SNR for higher input frequencies.

Quantization noise is also a limiting factor for SNR, as the theoretical maximum achievable SNR as a function of

the number of bits of resolution is set by Equation 1.

where

•

N = number of bits resolution

(1)

For a 14-bit ADC, the maximum SNR = 1.76 + (6.02 × 14) = 86.04 dB. This is the number that we shall enter into

Equation 2 for quantization noise as we solve for total SNR for different amounts of clock jitter using Equation 2.

(2)

The SNR limitation due to sample clock jitter can be calculated using Equation 3:

(3)

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