ADS5474IPFPR datasheet(20/41 Pages) TI1

20 / 41 page

CLK

ADS5474

CLK

SquareWaveor

SineWave

0.01 F

ClockAmplitude

0.5

1.0

1.5

5.0

2.0

2.5

3.0

f =400MSPS

=230MHz

3.5

4.0

4.5

SFDR(dBc)

SNR(dBFS)

1000 W

~ 2.4 V

CLK

AVDD5

1000 W

GND

ADS5474

GND

~ 2.5 nH Bond Wire

Parasitic

~0.2pF

Parasitic

~0.2pF

S0292-04

Internal

Clock

Buffer

~ 0.5pF

Package

~ 0.5pF

Package

~ 200fF

BondPad

~ 200fF

BondPad

ADS5474

SLAS525C – JULY 2007 – REVISED JANUARY 2016

www.ti.com

Feature Description (continued)

Figure 35. Clock Input Circuit

Figure 36. Single-Ended Clock

Figure 37. AC Performance vs Clock Level

7.3.2 Digital Outputs

The ADC provides 14 LVDS-compatible, offset binary data outputs (D13 to D0; D13 is the MSB and D0 is the

LSB), a data-ready signal (DRY), and an over-range indicator (OVR). TI recommends using the DRY signal to

capture the output data of the ADS5474 device. DRY is source-synchronous to the DATA/OVR outputs and

operates at the same frequency, creating a half-rate DDR interface that updates data on both the rising and

falling edges of DRY. It is recommended that the capacitive loading on the digital outputs be minimized. Higher

capacitance shortens the data-valid timing window. The values given for timing (see Figure 1) were obtained with

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