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ADS5474IPFPR Datasheet(PDF) 19 Page - Texas Instruments

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Part # ADS5474IPFPR
Description  14-Bit, 400-MSPS Analog-to-Digital Converter
PDF  41 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADS5474IPFPR Datasheet(HTML) 19 Page - Texas Instruments

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background image
500 W
500 W
Buffer
VCM
Buffer
1.6 pF
1.6pF
GND
S0293-01
AIN
AIN
AVDD5
AVDD5
ADS5463/5474/54RF63
GND
GND
~ 2.5 nH Bond Wire
~ 2.5 nH Bond Wire
~ 0.5pF
Package
~ 0.5pF
Package
~ 200fF
BondPad
~ 200fF
BondPad
ADS5474
www.ti.com
SLAS525C – JULY 2007 – REVISED JANUARY 2016
Feature Description (continued)
Figure 34. Analog Input Equivalent Circuit
For a full-scale differential input, each of the differential lines of the input signal (pins 16 and 17) swings
symmetrically between (3.1 V + 0.55 V) and (3.1 V – 0.55 V). This range means that each input has a maximum
signal swing of 1.1 VPP for a total differential input signal swing of 2.2 VPP. Operation below 2.2 VPP is allowable,
with the characteristics of performance versus input amplitude demonstrated in Figure 18 and Figure 19. For
instance, for performance at 1.1 VPP rather than 2.2 VPP, refer to the SNR and SFDR at –6 dBFS (0 dBFS =
2.2 VPP). The maximum swing is determined by the internal reference voltage generator, eliminating the need for
any external circuitry for this purpose.
7.3.1 Clock Inputs
The ADS5474 device clock input can be driven with either a differential clock signal or a single-ended clock
input. The characterization of the ADS5474 device is typically performed with a 3-VPP differential clock, but the
ADC performs well with a differential clock amplitude down to approximately 0.5 VPP, as shown in Figure 37. The
clock amplitude becomes more of a factor in performance as the analog input frequency increases. In low-input-
frequency applications, where jitter may not be a big concern, the use of a single-ended clock could save cost
and board space without much performance tradeoff. When clocked with this configuration, it is best to connect
CLK to ground with a 0.01-
μF capacitor, while CLK is ac-coupled with a 0.01-μF capacitor to the clock source, as
shown in Figure 36.
Copyright © 2007–2016, Texas Instruments Incorporated
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