ADS5474

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SLAS525C – JULY 2007 – REVISED JANUARY 2016

10 Layout

10.1 Layout Guidelines

The evaluation board represents a good model of how to lay out the printed circuit board (PCB) to obtain the

maximum performance from the ADS5474 device. Follow general design rules such as the use of multilayer

boards, a single ground plane for ADC ground connections, and local decoupling ceramic chip capacitors. The

analog input traces should be isolated from any external source of interference or noise, including the digital

outputs as well as the clock traces. The clock signal traces should also be isolated from other signals, especially

in applications such as high IF sampling where low jitter is required. Besides performance-oriented rules, care

must be taken when considering the heat dissipation of the device. The thermal heatsink included on the bottom

of the package should be soldered to the board as described in the PowerPad Package section. See the

ADS5474 EVM User Guide (SLAU194) on the TI web site for the evaluation board schematic.

10.1.1 PowerPAD Package

The PowerPAD package is a thermally-enhanced, standard-size IC package designed to eliminate the use of

bulky heatsinks and slugs traditionally used in thermal packages. This package can be easily mounted using

standard PCB assembly techniques, and can be removed and replaced using standard repair procedures.

The PowerPAD package is designed so that the leadframe die pad (or thermal pad) is exposed on the bottom of

the IC. This pad design provides an extremely low thermal resistance path between the die and the exterior of

the package. The thermal pad on the bottom of the IC can then be soldered directly to the PCB, using the PCB

as a heatsink.

10.1.1.1 Assembly Process

1. Prepare the PCB top-side etch pattern including etch for the leads as well as the thermal pad as illustrated in

the Mechanical Data section (at the end of this data sheet).

2. Place a 6 × 6 array of thermal vias in the thermal pad area. These holes should be 13 mils (0.013 in or

0.3302 mm) in diameter. The small size prevents wicking of the solder through the holes.

3. It is recommended to place a small number of 25-mil (0.025-in or 0.635-mm) diameter holes under the

package, but outside the thermal pad area, to provide an additional heat path.

4. Connect all holes (both those inside and outside the thermal pad area) to an internal copper plane (such as a

ground plane).

5. Do not use the typical web or spoke via-connection pattern when connecting the thermal vias to the ground

plane. The spoke pattern increases the thermal resistance to the ground plane.

6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area.

7. Cover the entire bottom side of the PowerPAD vias to prevent solder wicking.

8. Apply solder paste to the exposed thermal pad area and all of the package terminals.

For more detailed information regarding the PowerPAD package and its thermal properties, see either the

PowerPAD Made Easy application brief (SLMA004) or the PowerPAD Thermally Enhanced Package application

report (SLMA002), both available for download at www.ti.com.

Copyright © 2007–2016, Texas Instruments Incorporated

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