VS6955CA datasheet(59/90 Pages) STMICROELECTRONICS

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VS6955CA

Video timing

Figure 21. Output size within a CCP data frame

Note:

CCP2 requires that the CCP output active line length (between start and end sync codes)

for RAW8 is a multiple of 4 and for RAW10 is a multiple of 16.

CSI-2 requires that RAW8 is a multiple of 2 pixels (actual definition is 1 pixel but 2 are

required to preserve the Bayer pattern) and RAW10 is a multiple of 4 pixels (40 bits).

The host must control the x_output_size to ensure that the CCP output active line length

meets the above criteria.

7.1.8

PLL block

The VS6955CA contains a phase locked loop (PLL) block, which generates all the

necessary internal clocks from the external clock input. Changes to the PLL settings on the

VS6955CA are only consumed on the software standby to streaming mode transition.

Figure 22 shows the internal functional blocks, which define the relationship between the

external input clock frequency and the pixel clock frequency.

The majority of the logic within the device is clocked by vt_sys_clk however the CCI block is

clocked by the external input clock.

CCP output active line length

Interframe padding

x_output_size

Output data

Embedded data lines

VS6955CA Datasheet(PDF) 59 Page - STMicroelectronics