VS6955CA datasheet(35/90 Pages) STMICROELECTRONICS

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VS6955CA

Camera control interface (CCI)

4.2.11

CSI2 registers [0x808]

4.2.12

DPHY registers [0x820 to 0x823]

4.2.13

Binning registers [0x900 to 0x902]

Table 19. CSI2 registers [0x808]

Index

Byte

Data

type

Default

Type

Comment

0808

dphy_ctrl

8UI

CSI2 DPHY control

1 = Use UI control.

2 = Use register control.

Table 20. DPHY registers [0x820 to 0x823]

Index

Byte

Data

type

Default

Type

Comment

0820

dphy_channel_mbps_for_ui

32UR

00.00

CSI2 DPHY requested (target)

channel rate in Mbps (16.16 fixed-

point representation)

This is used to calculate the DPHY

unit-interval (UI) value.

It does not control the sensor clock

setup, but should normally

correspond to those settings.

0 = Sensor automatically calculates

UI from host-programmed EXTCLK

and clock divider values and reports

in MAN_SPEC_DPHY__CLKLANE_

UIX4 register.

80-1000 = Sensor calculates UI from

Mbps value.

0821

3rd

0822

2nd

0823

Table 21. Binning registers [0x900 to 0x902]

Index

Byte

Data

type

Default

Type

Comment

0900

binning_mode

8UI

Binning mode.

0 = Disabled

1 = Enabled

0901

binning_type

8UI

High-nibble = Column binning factor.

High-nibble = Row binning factor.

0902

binning_weighting

8UI

Binning weighting type:

0 = Averaged.

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