VS6955CA datasheet(31/90 Pages) STMICROELECTRONICS

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VS6955CA

Camera control interface (CCI)

4.2.7

Video timing registers [0x0300 to 0x0387]

For a full description of the video timing registers refer to Chapter 6: Video data interface on

page 49.

Table 15. Video timing registers [0x0300 to 0x0387]

Index

Byte

Data

type

Default

Type

Comment

0300

vt_pix_clk_div

16UI

Video timing pixel clock divider.

0301

0302

vt_sys_clk_div

16UI

Video timing system clock divider.

Note: This value must be even for

single lane modules

0303

0304

pre_pll_div

16UI

Pre-PLL clock divider value.

0305

0306

pll_mult

16UI

PLL multiplier value.

Odd and even values can be used,

but odd values result in the nearest

lower even value being used (for

example, 133 becomes 132).

0307

0308

op_pix_clk_div

16UI

Output timing pixel clock divider.

0309

030A

op_sys_clk_div

16UI

Output timing system clock divider.

Note: This value must be even for

single lane modules

030B

0340

frame_length_req

16UI

Length of the video frame in lines.

0341

0342

line_length_req

16UI

Length of a line of video in pixels.

0343

0344

x_start_req

16UI

X pixel address of the top left corner

of the visible pixel data.

0345

0346

y_start_req

16UI

Y line address of the top left corner of

the visible pixel data.

0347

0348

x_end_req

16UI

X pixel address of the bottom right

corner of the visible pixel data.

0349

034A

y_end_req

16UI

Y line address of bottom right corner

of the visible pixel data.

034B

034C

x_op_size_req

16UI

Width in pixels of the output image

from the sensor.

034D

034E

y_op_size_req

16UI

Height in lines of the output image

from the sensor.

034F

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