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VS6955CA Datasheet(PDF) 77 Page - STMicroelectronics |
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VS6955CA Datasheet(HTML) 77 Page - STMicroelectronics |
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77 / 90 page  DocID028071 Rev 2 77/90 VS6955CA Electrical characteristics 78 10.4.3 EXTCLK - timing characteristics Figure 33. External clock timing 10.4.4 CCI interface - timing characteristics Table 47. External clock timing characteristics Symbol Parameter Minimum Maximum Unit Tjitter Input clock jitter - 100 ps EXTCLK Tjitter Table 48. CCI interface timing characteristics Symbol Parameter Minimum Maximum Unit tSCL SCL clock frequency 0 400 kHz tLOW Clock pulse width low 1.3 - ms tHIGH Clock pulse width high 0.6 - ms tBUF Bus free time between transmissions 1.3 - ms tHD.STA Start hold time 0.6 - ms tSU.STA Start set-up time 0.6 - ms tHD.DAT Data in hold time 0 0.9 ms tSU.DAT Data in set-up time 100 - ns tR SCL/SDA rise time 20+0.1 Cb (1) 1. Cb = total capacitance of one bus line in pF 300 ns tF SCL/SDA fall time 20+0.1 Cb (1) 300 ns tSU.STO Stop set-up time 0.6 - ms Ci/o Input/output capacitance (SDA) - 8 pF Cin Input capacitance (SCL) - 6 pF |
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