TAS3103 datasheet(49/146 Pages) TI

49 / 146 page

2−17

In the I2C master mode, data rate transfer is fixed at 100 kHz, assuming MCLKI or XTALI = 12.288 MHz, PLL0 = PLL1

= 0, and MICROCLK_DIV = 0. In the I2C slave mode, data rate transfer is determined by the master device. However,

the setting of I2C parameter N at subaddress 0xFB (see the PLL and Clock Management section) does play a role

in setting the data transfer rate. In the I2C slave mode, bit rates other than (and including) the I2C-specific 100K-bps

and 400K-bps bit rates can be obtained, but N must always be set so that the over-sample clock into the I2C

master/slave controller is at least a factor of 10 higher in frequency than SCL.

The I2C communication protocol for the I2C slave mode is shown in Figure 2−15.

I2C_SDA

I2C_SCL

1†

Start

(By Master)

Slave Address

(By Master)

0†

Read or Write

(By Master)

Acknowledge

(By TAS3103)

Data Byte

(By Transmitter)

Acknowledge

(By Receiver)

Data Byte

(By Transmitter)

Acknowledge

(By Receiver)

Stop

(By Master)

MSB

MSB−1 MSB−2

LSB

Start Condition

I2C_SDA

↓ While I2C_SCL = 1

Stop Condition

I2C_SDA

↑ While I2C_SCL = 1

† Bits CS1 and CS0 in the TAS3103 slave address are compared to the logic levels on pins CS0 and CS1 for address verification. This provides

the ability to address up to four TAS3103 chips on the same I2C bus.

Figure 2−15. I2C Slave Mode Communication Protocol

In the slave mode, the I2C bus is used to:

•

Update coefficient values and output data to those GPIO ports configured as output.

•

Read status flags, input data from those GPIO ports configured as inputs and retrieve spectrum

analyzer/VU meter data.

In the master mode, the I2C bus is used to download a user-specific configuration from an I2C compatible EEPROM.

In the slave mode only, specific registers and memory locations in the TAS3103 are accessible with the use of I2C

subaddresses. There are 256 such I2C subaddresses. The protocol required to access a specific subaddress is

presented in Figure 2−16.

As shown in Figure 2−16, a read transaction requires that the master device first issue a write transaction to give the

TAS3103 the subaddress to be used in the read transaction that follows. This subaddress assignment write

transaction is then followed by the read transaction. For write transactions, the subaddress is supplied in the first byte

of data written, and this byte is followed by the data to be written. For write transactions, the subaddress must always

be included in the data written. There cannot be a separate write transaction to supply the subaddress, as was

required for read transactions. If a subaddress assignment only write transaction is followed by a second write

transaction supplying the data, erroneous behavior results. The first byte in the second write transaction is interpreted

by the TAS3103 as another subaddress replacing the one previously written.

TAS3103 Datasheet(PDF) 49 Page - Texas Instruments

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