TAS3103 datasheet(13/146 Pages) TI

13 / 146 page

1−5

1.5

Ordering Information

PLASTIC

38-PIN TSSOP

(DBT)

°C to 70°C

TAS3103DBT

−40

°C to 85°C

TAS3103IDBT

1.6

Terminal Functions

TERMINAL

DESCRIPTION

PULLUP/

(2)

NAME

NO.

I/O

TYPE(1)

DESCRIPTION

PULLUP/

DOWN(2)

A_VDDS (3.3 V)

PWR

The PWR pin is used to input 3.3-V power to the DPLL and clock oscillator.

This pin can be connected to the same power source used to drive the DVSS

power pin. To achieve low DPLL jitter, this pin should be bypassed to AVSS

with a 0.01-

µF capacitor (low ESR preferable).

None

AVDD_BYPASS_CAP

PWR

AVDD_BYPASS_CAP is a pinout of the internally regulated 1.8-VDC power

used by the DPLL and crystal oscillator. This pin should be connected to pin 8

with a 0.01-

µF capacitor (low ESR preferable). This pin must not be used to

power external devices.

None

AVSS

PWR

AVSS is the ground reference for the internal DPLL and oscillator circuitry.

This pin needs to reference the same ground as DVSS power pin. To achieve

low DPLL jitter, ground noise at this pin must be minimized. The availability of

the AVSS pin allows a designer to use optimizing techniques such as star

ground connections, separate ground planes, or other quiet ground

distribution techniques to achieve a quiet ground reference at this pin.

None

CS0

CS0 is the LSB of a 2-bit code used to generate part of an I2C device address

that makes it possible to address four TAS3103 ICs on the same bus without

additional chip select logic. The pulldowns on the inputs select 00 as a default

when neither pin is connected.

Pulldown

CS1

CS1 is the MSB of a 2-bit code used to generate part of an I2C device address

that makes it possible to address four TAS3103 ICs on the same bus without

additional chip select logic.

Pulldown

DVDD_BYPASS_CAP

PWR

DVDD_BYPASS_CAP is a pin-out of the internally regulated 1.8-V power

used by all internal digital logic. This pin must not be used to power external

devices. A low ESR capacitor of at least 470 nF should be placed as close to

the device as possible between this pin and pin 28.

None

DVSS

PWR

DVSS is the digital ground pin.

None

GPIO0

I/O

GPIO0 is a general-purpose I/O, controlled by the internal microprocessor

through I2C commands. When in the I2C master mode, GPIO0 serves as a

volume up command for CH1/CH2.

Pullup

GPIO1

I/O

GPIO1 is a general-purpose I/O, controlled by the internal microprocessor

through I2C commands. When in the I2C master mode, GPIO1 serves as a

volume down command for CH1/CH2.

Pullup

GPIO2

I/O

GPIO2 is a general-purpose I/O, controlled by the internal microprocessor

through I2C commands. When in the I2C master mode, GPIO2 serves as a

volume up command for CH3.

Pullup

GPIO3

I/O

GPIO3 is a general-purpose I/O, controlled by the internal microprocessor

through I2C commands. When in the I2C master mode, GPIO3 serves as a

volume down command for CH3.

Pullup

I2CM_S

I2CM_S is a non-latched input that determines whether the TAS3103 acts as

an I2C master or slave. Logic high, or no connection, sets the TAS3103 as an

I2C master device. A logic low sets the TAS3103 as an I2C slave device. As a

master I2C device, the TAS3103 I2C port must have access to an external

EEPROM for input.

Pullup

TAS3103 Datasheet(PDF) 13 Page - Texas Instruments

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