TAS3103 datasheet(53/146 Pages) TI

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2−21

Table 2−5. Four Byte Read Exceptions—Reserved and Factory-Test I2C Subaddresses

SUB-ADDRESS

NUMBER BYTES SUPPLIED BY TAS3103

0xC9

0xED

NOTE: Table 2−5 does not include read-only subaddresses and thus does

not include subaddresses 0xFD, 0xFE, and 0xFF. When read, these

read-only subaddresses output 10, 2, and 1 byte respectively.

Thus, for all reserved and factory-test subaddresses, except subaddresses OxC9 and 0xED, the master device must

issue four data received acknowledges for the four bytes of zero-valued data. For subaddresses OxC9 and 0xED,

the master device must issue eight data received acknowledges for the eight bytes of zero-valued data.

Sequential read transactions do not have restrictions on outputting only complete subaddress data sets. If the master

does not issue enough data received acknowledges to receive all the data for a given subaddress, the master device

simply does not receive all the data. If the master device issues more data received acknowledges than required to

receive the data for a given subaddress, the master device simply receives complete or partial sets of data, depending

on how many data received acknowledges are issued from the subaddress(es) that follow.

I2C read transactions, both sequential and random, can impose wait states. For the standard I2C mode

(SCL = 100 kHz), worst-case wait state times for an 8-MHz microprocessor clock is on the order of 2

µs. Nominal

wait state times for the same 8-MHz microprocessor clock is on the order of 1

µs. For the fast I2C mode (SCL =

400 kHz) and the same 8-MHz microprocessor clock, worst-case wait state times can extend up to 10.5

µs in duration.

Nominal wait state times for this same case lie in a range from 2

µs to 4.6 µs. Increasing the microprocessor clock

frequency lowers the wait state times and for the standard I2C mode, a higher microprocessor clock can totally

eliminate the presence of wait states. For example, increasing the microprocessor clock to 16 MHz results in no wait

states. For the fast I2C mode, higher microprocessor clocks shortens the wait state times encountered, but does not

totally eliminate their presence.

2.4

Digital Audio Processor (DAP) Arithmetic Unit

The digital audio processor (DAP) arithmetic unit is a fixed-point computational engine consisting of an arithmetic unit

and data and coefficient memory blocks. Figure 2−17 is a block diagram of the arithmetic unit.

76-Bit Adder

Regs

Arithmetic

Engine

Dual Port

Data RAM

Coefficient

RAM

4K x 16

Delay Line

RAM

Program

ROM

DAP

Instruction Decoder/Sequencer

Digital Audio Processor

(DAP)

Arithmetic Unit

Figure 2−17. Digital Audio Processor Arithmetic Unit Block Diagram

The DAP arithmetic unit is used to implement all firmware functions—soft volume, loudness compensation, bass and

treble processing, dynamic range control, channel filtering, 3D effects, input and output mixing, spectrum analyzer,

VU meter, and dither.

Figure 2−18 shows the data word structure of the DAP arithmetic unit. Eight bits of overhead or guard bits are provided

at the upper end of the 48-bit DAP word and 8 bits of computational precision or noise bits are provided at the lower

end of the 48-bit word. The incoming digital audio words are all positioned with the most significant bit abutting the

8-bit overhead/guard boundary. The sign bit in bit 39 indicates that all incoming audio samples are treated as signed

data samples.

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