DP83266 datasheet(34/152 Pages) NSC

34 / 152 page

60 Functional Description (Service Engine) (Continued)

current transaction Note that Bus Request is guaranteed to

be de-asserted for at least two cycles when MR1EAM is

enabled It is a requirement of the SBus specification that

Bus Request be de-asserted between each transaction If

Bus Grant is (re)asserted before the end of the current

transaction the MACSI device retains mastership and runs

the next transaction This process may be repeated indefi-

nitely

It is important to note that in default ABus mode (MR1EAM

0) the MACSI device may take up to two cycles to detect

the assertion of Bus Grant Therefore the external interface

logic must not remove Bus Grant or latch addresses until a

signal such as Address Strobe is asserted indicating that

the MACSI device has recognized the Bus Grant

If the Bus Arbiter wishes to preempt the MACSI device it

deasserts Bus Grant The MACSI device will complete the

current bus transaction then release the bus From preemp-

tion to bus release is a maximum of (11 bus clocks a

(8 times the number of memory wait states)) bus clocks For

example in a 1 wait-state system the MACSI device will

release the bus within a maximum of 19 bus clocks

Parity

The state of the FLOW bit in System Interface Mode Regis-

ter 0 (SIMR0FLOW) controls two MACSI device modes

one for systems using parity the other for systems not using

parity

Regardless of the state of SIMR0FLOW the MACSI device

always provides odd parity on ABus address cycles and

Control Bus read cycles The MACSI device System Inter-

face does not check data parity on ABus read cycles The

User may enable checking of read data parity at the Ring

Engine interface by setting the MAC Request Parity bit

(MCMR0MRP) For MACSI revision D or later the System

Interface will check parity on descriptor reads (when

SIMR0FLOW e 1) and report errors via the STARERR bit

The ABus data parity (except for Descriptor data parity

which is generated internally) flows directly from the Ring

Engine interface If parity checking is enabled within the

Ring Engine parity flows up from the PLAYERa interface

If parity checking is disabled within the Ring Engine good

parity is generated at the Ring EngineService Engine inter-

face

For transmit frame data the parity from the ABus flows di-

rectly to the Ring Engine interface when SIMR0FLOW is

asserted The data integrity across the ABus and through

the Service Engine may be checked by enabling parity

checking within the Ring Engine If the SIMR0FLOW bit is

deasserted the MACSI device will generate good parity at

the transmit data (MR7 – 0) Ring Engine interface

When SIMR0FLOW is enabled parity is checked on Con-

trol Bus write operations If a parity error is detected the

write access is rejected and the STARCPE bit is asserted

When SIMR0FLOW is disabled Control Bus write parity is

ignored

When SIMR0FLOW is enabled parity is checked on MAC

Indicate interface (receive data from the Ring Engine) If an

error is detected the STARBPE will be asserted and the

IDUD for that frame will carry a status of ‘‘parity error’’

When SIMR0FLOW is disabled the parity bit at the MAC

Indicate interface is ignored

Bandwidth

The ABus supports single reads and writes and burst reads

and writes With physical addressing back-to-back single

readswrites can take place every four clock cycles Burst

transactions can transfer 8 32-bit words (32 bytes) every 11

clock cycles With a 25 MHz clock this yields a peak band-

width of 727 Mbytessec

To allow the bus to operate at high frequency the protocol

defines all signals to be both asserted and deasserted by

the bus master and slaves Having a bus device actively

deassert a signal guarantees a high-speed inactive tran-

sition If this were not defined external pull-up resistors

would not be able to deassert signals fast enough The pro-

tocol also reduces contention by avoiding cases where two

bus devices simultaneously drive the same line

The MACSI device operates synchronously with the ABus

clock In general operations will be asynchronous to the

ring since most applications will use a system bus clock

that is asynchronous to the ring The MACSI device is de-

signed to interface either directly to the host’s main system

bus or to external shared memory When interfaced to the

host’s bus there are two parameters of critical interest la-

tency and bandwidth

Data moves between the Request and Indicate Channels

and the ABus via four FIFOs two in the receive path (Indi-

cate) and two in the transmit path (Request) There are two

1152 x 36-bit data FIFOs for Indicate and Request data

(4608 byte of data FIFO in each direction) On the ABus

Interface there are two Burst FIFOs each containing two

banks of 32 bytes which provide ABus bursting capability

The amount of latency covered by the Data FIFO plus one

of the banks of the Burst FIFO must meet the average and

maximum bus latencies of the external memory With a new

byte every 80 ns from the ring a 4608 byte FIFO provides

4608 c 80 ns e 36864 ms maximum latency The two 32

byte burst FIFO in each direction provide an additional

51 ms of latency

To assist latency issues the MACSI device can completely

empty or fill the Burst FIFO in one bus tenure by asserting

Bus Request for multiple transactions Since one bank of

the Burst FIFO is 8 words deep if 8-word bursts are en-

abled that half of the Burst FIFO can be emptied in one

transaction If the second half of the burst FIFO is also full it

can be emptied in the same bus tenure by again granting

the bus to the MACSI device

The MACSI device may be preempted at any time by remov-

ing Bus Grant causing the MACSI device to complete the

current transaction and release the bus There will be a

maximum of 11 clocks (plus any memory wait states) from

preemption to bus release (fewer if 8-word bursts are not

enabled)

642 Bus States

An ABus Master has eight states idle (Ti) bus request

(Tbr) virtual address (Tva) MMU translate (Tmmu) physical

address (Tpa) data transfer (Td) wait (Tw) and recovery

(Tr)

An ABus Slave has five states idle (Ti) selected (Ts) data

transfer (Td) wait (Tw) and recovery (Tr)

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