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DP83266 Datasheet(PDF) 63 Page - National Semiconductor (TI) |
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DP83266 Datasheet(HTML) 63 Page - National Semiconductor (TI) |
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63 / 152 page  70 Control Information (Continued) Ring Event Mask Register 1 (REMR1) Ring Event Mask Register 1 is used to mask bits in Register RELR1 If a bit in Register REMR1 is set to One the corresponding bit in Register RELR1 will be applied to the Interrupt Condition Register which can then be used to generate an interrupt to the CPU All bits in this register are set to Zero upon reset Access Rules Address Read Write 013h Always Always Register Bits D7 D6 D5 D4 D3 D2 D1 D0 LOCLM HICLM MYCLM RES RES RES MYBCN OTRBCN Bit Symbol Description D7 LOCLM Lower Claim Mask This bit is used to mask RELR1LOCLM D6 HICLM Higher Claim Mask This bit is used to mask RELR1HICLM D5 MYCLM My Claim Mask This bit is used to mask RELR1MYCLM D4 – D2 RES Reserved D1 MYBCN My Beacon Mask This bit is used to mask RELR1MYBCN D0 OTRBCN Other Beacon Mask This bit is used to mask RELR1OTRBCN 63 |
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