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DP83266 Datasheet(PDF) 100 Page - National Semiconductor (TI) |
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DP83266 Datasheet(HTML) 100 Page - National Semiconductor (TI) |
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100 / 152 page  70 Control Information (Continued) No Space Notify Register (NSNR) The No Space Notify Register (NSNR) is used to enable attentions in the No Space Attention Register (NSAR) If a bit in Register NSNR is set to One the corresponding bit in Register NSAR will be applied to the Master Attention Register which can be used to generate an interrupt to the host All bits in this register are set to Zero upon reset Access Rules Address Read Write 10Bh Always Always Register Bits D7 D6 D5 D4 D3 D2 D1 D0 NSR0N NSR1N LDI0N NSI0N LDI1N NSI1N LDI2N NSI2N Bit Symbol Description D0 NSI2N No Status Space on ICHN2 Notify This bit is used to enable the NSI2 bit in Register NSAR D1 LDI2N Low Data Space on ICHN2 Notify This bit is used to enable the LDI2 bit in Register NSAR D2 NSI1N No Status Space on ICHN2 Notify This bit is used to enable the NSI1 bit in Register NSAR D3 LDI1N Low Data Space on ICHN2 Notify This bit is used to enable the LDI1 bit in Register NSAR D4 NSI0N No Status Space on ICHN2 Notify This bit is used to enable the NSI0 bit in Register NSAR D5 LDI0N Low Data Space on ICHN2 Notify This bit is used to enable the LDI0 bit in Register NSAR D6 NSR1N No Status Space on ICHN2 Notify This bit is used to enable the NSR1 bit in Register NSAR D7 NSR0N Low Data Space on ICHN2 Notify This bit is used to enable the NSR0 bit in Register NSAR Limit Address Register (LAR) The Limit Address Register (LAR) is used to program the parameters for an LMOP (Limit RAM Operation) service function This register is not altered upon reset Access Rules Address Read Write 10Ch Always Always Register Bits D7 D6 D5 D4 D3 D2 D1 D0 LRA3 LRA2 LRA1 LRA0 LMRW RES RES LRD8 Bit Symbol Description D0 LRD8 Limit RAM Data Bit 8 This bit contains the most-significant data bit read or written from the addressed limit RAM Register Bits LDR8 and LDR7 are ‘‘don’t cares’’ when using small (1 kByte) queues D2 – D1 RES Reserved D3 LMRW LMOP ReadWrite This bit determines whether a LMOP service function will be a read (LMRW) e 1) or write (LMRW e 0) D4 – D7 LRA3 – LRA0 Limit RAM Register Address Used to program the Limit RAM Register address for a subsequent LMOP service function 100 |
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