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DP83266 Datasheet(PDF) 42 Page - National Semiconductor (TI) |
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DP83266 Datasheet(HTML) 42 Page - National Semiconductor (TI) |
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42 / 152 page  60 Functional Description (Service Engine) (Continued) TLF11705 – 16 FIGURE 6-11 Enhanced ABus Mode Back-to-Back Read Timing Burst Read Tbr MACSI device asserts AB BR to indicate it wishes to perform a transfer Host asserts AB BG The MACSI de- vice moves to Tma in the next cycle This cycle may be skipped if AB BR was asserted during the previous ac- cess This allows for back-to-back burst reads Tma MACSI device drives AB A and AB AD with the master address asserts AB AS drives AB RW and AB SIZ 20 and negates AB BR for at least two cycles Tpa The Physical Address is asserted by the MMU Td MACSI device samples AB ACK AB ERR and AB DEN and increments the address on AB A Slave acknowledges using AB ACK AB ERR and AD DEN MACSI device samples a valid AB ACK and latches data in the following cycle Tw states may occur after Td Td state is repeated four or eight times (according to the burst size) If SIMR1ASM e 0 the MACSI device negates AB AS in the last Td cycle If SIMR1ASM e 1 the MACSI device negates AB AS in the first Td cycle Tr MACSI device negates AB RW and AB SIZ 20 and releases AB A and AB AS Slave drives AB AD (with data) deasserts AB ACK AB ERR and AB DEN Ifan- other request is pending (AB BR asserted) and the Bus is regranted in this cycle the MACSI device will proceed di- rectly to the Tma state of the next burst The normal Tbr state is skipped allowing back-to-back burst reads Burst Write Tbr MACSI device asserts AB BR to indicate it wishes to perform a transfer Host asserts AB BG The MACSI de- vice moves to Tma in the next cycle Tma MACSI device drives AB A and AB AD with the master address asserts AB AS drives AB RW and AB SIZ 20 and negates AB BR until this transaction is completed Tpa The Physical Address is asserted by the MMU Td MACSI device drives AB AD with the write data sam- ples AB ACK AB ERR and AB DEN and increments the address on AB A Slave captures AB AD data and acknowledges using AB ACK AB ERR and AB DEN MACSI device samples a valid acknowledge Tw states may occur after Td Td state is repeated as required for the com- plete burst If SIMR1ASM e 0 the MACSI device negates AB AS in the last Td cycle If SIMR1ASM e 1 the MACSI device negates AB AS in the first Td cycle Tr MACSI device negates AB RW AB SIZ 20 releas- es AB A and AB AS and stops driving AB AD with data Slave deasserts AB ACK AB ERR and AB DEN 42 |
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