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DP83266 Datasheet(PDF) 74 Page - National Semiconductor (TI) |
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DP83266 Datasheet(HTML) 74 Page - National Semiconductor (TI) |
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74 / 152 page  70 Control Information (Continued) Interrupt Mask Register (IMR) The Interrupt Mask Register (IMR) is used to mask bits in the Interrupt Condition Register (ICR) If a bit in Register IMR and the corresponding bit in Register ICR are set to One the INT0 pin is forced low and causes an interrupt Each bit in the IMR corresponds to an Event Register or a pair of Event Registers and associated bits Access Rules Address Read Write 02Fh Always Always Register Bits D7 D6 D5 D4 D3 D2 D1 D0 ESE IERR RES RES COE CIE TTE RNG Bit Symbol Description D7 ESE Exception Status Event Mask This bit is used to mask ICRESE D6 IERR Internal Error Mask This bit is used to mask ICRIERR D5 – D4 RES Reserved D3 COE Counter Overflow Event Mask This bit is used to mask ICRCOE D2 CIE Counter Increment Event Mask This bit is used to mask ICRCIE D1 TTE Token and Timer Event Mask This bit is used to mask ICRTTE D0 RNG Ring Event Mask This bit is used to mask ICRRNG 74 |
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