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DP83266 Datasheet(PDF) 60 Page - National Semiconductor (TI) |
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DP83266 Datasheet(HTML) 60 Page - National Semiconductor (TI) |
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60 / 152 page ![]() 70 Control Information (Continued) Current Transmitter Status Register (CTS0) The Current Transmitter Status Register (CTS0) records the status of the Transmitter state machine It is continuously updated It remains stable when accessed When in Diagnose Mode this register is frozen on an internal error until the internal error event is cleared by resetting the TSMERR bit in the Internal Event Latch Register Access Rules Address Read Write 00Eh Always Data Ignored Register Bits D7 D6 D5 D4 D3 D2 D1 D0 ROP TS2 TS1 TS0 TTS3 TTS2 TTS1 TTS0 Bit Symbol Description D7 ROP Ring Operational Flag Indicates the current value of the local Ring Operational Flag D6–D4 TS(2–0) Transmit State TS(2 – 0) represent the current state of the Transmit state machine that implements the ANSI X3T95 standard MAC Transmit Functions The encoding is shown below TS2 TS1 TS0 Transmit State 0 0 0 Idle 0 0 1 Repeat 0 1 0 Data 0 1 1 Issue Token 1 0 0 Claim 1 0 1 Beacon 1 1 0 Reserved 1 1 1 Void D3 – D0 TTS(3 – 0) Transmit Timing State TTS(3 – 0) represent the current state of the Transmit Timing state machine The encoding is shown below TTS3 TTS2 TTS1 TTS0 Transmit Timing State 0 0 0 0 Idle 0 0 0 1 Transmit Preamble 0 0 1 0 Wait for Data (FIFO) 0 0 1 1 Transmit SD and FC Fields 0 1 0 0 Transmit DA 0 1 0 1 Transmit SA 0 1 1 0 Transmit INFO 0 1 1 1 Transmit FCS 1 0 0 0 Transmit ED and FS 9h – Fh Reserved 60 |
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