DP83266 datasheet(43/152 Pages) NSC

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70 Control Information

71 OVERVIEW

The Control Information includes Operation Event Status

and Parameter Registers that are used to manage and op-

erate the MACSI Device A controller on the external Con-

trol Bus gains access to read and write these parameters

via the Control Bus Interface

The MACSI device combines the functions of the original

DP83261 BMAC device and the DP83265 BSI device with

many enhanced capabilities The MACSI device has addi-

tional Control Bus address lines compared to the BMAC and

BSI devices (CBA(80)) When the most significant address

bit (CBA8) is zero the internal BMAC register block is se-

lected When CBA8 is 1 the internal BSI register block is

selected The actual addresses within the MACSI device are

defined in Table 7-1 and Table 7-2

All registers and control bits within the BSI register block of

the MACSI device have the same relative addresses and

functions as they do in the BSI device All registers and

control bits within the BMAC register block of the MACSI

device have the same relative addresses and functions as

they do in the BMAC device The only exceptions to this are

shown in the detailed register descriptions following the

memory map table There are two registers which have new

features unique to the MACSI device or functions which are

slightly modified from the original BMAC or BSI device

These are MCMR0 and MCMR2

TABLE 7-1 MACSI Memory Map (BMAC Registers)

Address

Access Rules

Reset

Value

Read

Write

000

MAC Mode Register 0 (MCMR0)

Always

001

Option Register (Option)

Always

002

Function Register (Function)

Always

003

Reserved

004

Reserved

005

MAC Mode Register 2 (MCMR2)

Always

006

Reserved

007

MAC Revision (MCRev)

Always

Data Ignored

008

MAC Compare Register (MCCMP)

Always

009 – 00B

Reserved

00C

Current Receiver Status Register (CRS0)

Always

Data Ignored

00D

Reserved

00E

Current Transmitter Status Register (CTS0)

Always

Data Ignored

00F

Reserved

010

Ring Event Latch Register 0 (RELR0)

Always

Conditional

011

Ring Event Mask Register 0 (REMR0)

Always

012

Ring Event Latch Register 1 (RELR1)

Always

Conditional

013

Ring Event Mask Register 1 (REMR1)

Always

014

Token and Timer Event Latch Register (TELR0)

Always

Conditional

015

Token and Timer Event Mask Register (TEMR0)

Always

016 – 017

Reserved

018

Counter Increment Latch Register (CILR)

Always

Conditional

019

Counter Increment Mask Register (CIMR)

Always

01A – 01B

Reserved

01C

Counter Overflow Latch Register (COLR)

Always

Conditional

01D

Counter Overflow Mask Register (COMR)

Always

01E – 027

Reserved

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