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DP83266 Datasheet(PDF) 72 Page - National Semiconductor (TI) |
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DP83266 Datasheet(HTML) 72 Page - National Semiconductor (TI) |
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72 / 152 page  70 Control Information (Continued) Exception Mask Register (EMR) The Exception Mask Register (EMR) is used to mask bits in the Exception Status Register (ESR) If a bit in Register EMR is set to One the corresponding bit in Register ESR will be applied to the Condition Register which can then be used to generate an interrupt All bits in this register are set to Zero upon reset Access Rules Address Read Write 02Dh Always Always Register Bits D7 D6 D5 D4 D3 D2 D1 D0 ZERO CCE CPE RES RES RES RES PPE Bit Symbol Description D7 ZERO Zero This bit is always Zero This implies that the CWI bit never contributes to the Interrupt Signal D6 CCE Control Bus Error Mask This bit is used to mask ESRCCE D5 CPE Control Bus Parity Error Mask This bit is used to mask ESRCPE D4 – D1 RES Reserved D0 PPE PHY Interface Parity Error Mask This bit is used to mask ESRPPE 72 |
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