DP83266 datasheet(94/152 Pages) NSC

94 / 152 page

70 Control Information (Continued)

State Attention Register (STAR)

The State Attention Register (STAR) controls the state of the Indicate Request and StatusSpace Machines It also records

parity internal logic and ABus transaction errors Each bit may be enabled by setting the corresponding bit in the State Notify

This register is set to the value 07h upon reset

Access Rules

Address

Read

Write

106h

Always

Conditional

ERR

BPE

CPE

CWI

CMDE

SPSTOP

RQSTOP

INSTOP

Bit

Symbol

Description

INSTOP

Indicate Stop

This bit is set by the host to place the Indicate Machine in Stop Mode It is also set upon reset

Three different conditions cause the MACSI device to set this bit The first is an internal error This is caused

by a bad tag read out of the Indicate Data FIFO This is a hardware error The next condition is an invalid

state This is a hardware error where the Indicate Machine state bits contain an illegal pattern The final

condition is when the user programs an illegal header length for HeaderInfo sorting mode An invalid value is

any value less than four words

This bit is set by serious hardware failures or illegal software operations Therefore it is recommended that

the entire MACSI device be reset if this bit should get set during normal operation

RQSTOP

Request Stop

This bit is set by the host to place the Request Machine in Stop Mode It is also set upon

reset The MACSI device will set this bit if it detects that the Request Machine has entered an illegal state

This is a hardware error The MACSI device will also set this bit if an ABus error is detected during any

Request Operation This includes REQ ODUD and ODU fetches and CNF writes

This bit is set by serious hardware failures or ABus errors Therefore it is recommended that the entire MACSI

device be reset if this bit should get set during normal operation

SPSTOP

StatusSpace Stop

This bit is set by the host to place the StatusSpace Machine in Stop Mode It is also set

upon reset In addition the MACSI device will set this bit upon detecting an unrecoverable error An

unrecoverable error is an ABus error during a PSP fetch or a Pointer RAM Operation (PTOP) In STOP Mode

only PTOP or LMOP service functions may be performed

This bit is set by ABus errors during critical StatusSpace operations Therefore it is recommended that the

entire MACSI device be reset if this bit should get set during normal operation This reset should include

reloading of Pointer RAM values and restarting the PSP queues

CMDE

Command Error

Indicates that the host performed an invalid operation This occurs when an invalid value is

loaded into the Indicate Header Length Register (which also sets the INSTOP attention) This bit is cleared

upon reset

This bit is set when software performs an illegal operation This indicates either a software bug or the

improper operation of the processor Therefore it is recommended that the entire MACSI device be reset if

this bit should get set during normal operation

CWI

Conditional Write Inhibit

Indicates that at least one bit of the previous conditional write operation was not

written This bit is set unconditionally after each write to a conditional write register It is also set when the

value of the Compare Register is not equal to the value of the register that was accessed for a write before it

was written This may indicate that the accessed register has changed since it was last read This bit is

cleared after a successful conditional write CWI bit does not contribute to setting the STA bit of the Master

Attention Register because its associated Notify bit is always 0 This bit is cleared upon reset

CPE

Control Bus Parity Error

Indicates a parity error detected on CBD7 – 0 If there is a Control Bus parity error

during a host write the write is suppressed Control Bus parity errors are reported when flow-through parity is

enabled (the FLOW bit of the Mode Register is set) This bit is cleared upon reset

BPE

BMAC Device Parity Error

Indicates parity error detected on MID7 – 0 This bit is cleared upon reset This bit

is only set if FLOW (parity enable) is set and the error occurred on a frame that the MACSI device has

decided to copy or if it occurred before the copy decision was made

ERR

Error

This bit is set by the MACSI device when a non-recoverable error occurs This includes any ABus

transaction error or an internal state machine error For MACSI revision D or later a descriptor fetch parity

error will also set this bit if the User has enabled parity checking via the SIMR0FLOW bit This bit is cleared

upon reset

DP83266 Datasheet(PDF) 94 Page - National Semiconductor (TI)

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