ADF7020BCP datasheet(17/40 Pages) AD

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Preliminary Technical Data

ADF7020

Rev. PrH | Page 17 of 40

RSSI/AGC SECTION

The RSSI is implemented as a successive compression log amp

following the base-band channel filtering. The log amp achieves

±3 dB log linearity. It also doubles as a limiter to convert the

signal-to-digital levels for the FSK demodulator. The RSSI itself

is used for amplitude shift keying (ASK) demodulation. In ASK

mode, extra digital filtering is performed on the RSSI value.

Offset correction is achieved using a switched capacitor integra-

tor in feedback around the log amp. This uses the BB offset

clock divide. The RSSI level is converted for user readback and

digitally controlled AGC by an 80-level (7-bit) flash ADC. This

level can be converted to input power in dBm.

IFWR

LATCH

AAA

CLK

ADC

OFFSET

CORRECTION

RSSI

ASK

DEMOD

FSK

DEMOD

Figure 15. RSSI Block Diagram

RSSI Thresholds

When the RSSI is above AGC_HIGH_THRESHOLD, the gain is

reduced. When the RSSI is below AGC_LOW_THRESHOLD,

the gain is increased. A delay (AGC_DELAY) is programmed to

allow for settling of the loop. The user programs the two

threshold values (recommended defaults, 27 and 76) and the

delay (default, 10). The default AGC setup values should be

adequate for most applications. The threshold values must be

chosen to be more than 30 apart for the AGC to operate

correctly.

Offset Correction Clock

In Register 3, the user should set the BB offset clock divide bits

R3_DB(4:5) to give an offset clock between 1 MHz and 2 MHz,

where:

BBOS _CLK [Hz] = XTAL/(BBOS_CLK_DIVIDE)

BBOS_CLK_DIVIDE can be set to 4, 8, or 16.

AGC Information

In Register 9, the user should select automatic gain control by

selecting auto in R9_DB18 and auto in R9_DB19. The user

should then program AGC low threshold R9_DB(4:10) and

AGC high threshold R9_DB(11:17). The recommended/default

values for the low and high thresholds are 30 and 70, respec-

tively. In the AGC2 register the user should program the AGC

delay to be long enough to allow the loop to settle. The

recommended value is 10.

RSSI Formula (Converting to dBm)

Input_Power [dBm] = −110 dBm + (Readback_Code +

Gain_Mode_Correction ) × 0.5

where:

Readback_Code is given by Bits RV7 to RV1 in the readback

Gain_Mode_Correction is given by the values in Table 6.

LNA gain and filter gain (LG2/LG1, FG2/FG1) are also obtained

from the readback register.

Table 6. Gain Mode Correction Table

LNA Gain

(LG2, LG1)

Filter Gain

(FG2, FG1)

Gain Mode Correction

H (10)

M (01)

H (10)

M (01)

19 + 11 = 30

M (01)

L (00)

19 + 19 + 11 = 49

L (00)

19 + 19 + 19 + 11 = 68

An additional factor should be introduced to account for losses

in the front-end matching network/antenna.

FSK DEMODULATORS ON THE ADF7020

The two FSK demodulators on the ADF7020 are

•

FSK correlator/demodulator

•

Linear demodulator

Select these using the demod select bits, R4_DB(4:5).

FSK CORRELATOR/DEMODULATOR

The quadrature outputs of the IF filter are first limited and then

fed to a pair of digital frequency correlators that perform band-

pass filtering of the binary FSK frequencies at (IF + FDEV) and

(IF − FDEV). Data is recovered by comparing the output levels

from each of the two correlators. The performance of this

frequency discriminator approximates that of a matched filter

detector, which is known to provide optimum detection in the

presence of AWGN.

IF – FDEV

IF + FDEV

LIMITERS

DB(4:13)

DB(8:15)

DB(14)

Rx DATA

Rx CLK

SLICER

FREQUENCY CORRELATOR

Figure 16. FSK Correlator/Demodulator Block Diagram

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