Preliminary Technical Data

ADF7020

Rev. PrH | Page 33 of 40

REGISTER 6—CORRELATOR/DEMODULATOR REGISTER

DEMOD

RESET

CDR

RESET

DISCRIMINATOR BW

IF FILTER DIVIDER

Rx

RESET

ADDRESS

BITS

RI1

0

1

RxDATA

INVERT

RxDATA

RxDATA

CA1

0

1

FILTER CAL

NO CAL

CALIBRATE

ML1

0

1

MIXER LINEARITY

DEFAULT

HIGH

DP1

0

1

DOT PRODUCT

CROSS PRODUCT

DOT PRODUCT

LG1

0

1

LNA MODE

DEFAULT

REDUCED GAIN

FC3

0

0

.

.

.

.

1

FC1

1

0

.

.

.

.

1

FILTER CLOCK

DIVIDE RATIO

1

2

.

.

.

.

511

FC2

0

1

.

.

.

.

1

FC9

0

0

.

.

.

.

1

FC6

0

0

.

.

.

.

1

.

.

.

.

.

.

.

.

FC5

0

0

.

.

.

.

1

FC4

0

0

.

.

.

.

1

LI2

0

LI1

0

LNA BIAS

800

µA (DEFAULT)

Figure 34.

Notes:

1.

See the FSK Correlator/Demodulator section for an example of how to determine register settings.

2.

Nonadherence to correlator programming guidelines results in poorer sensitivity.

3.

The filter clock is used to calibrate the IF filter. The filter clock divide ratio should be adjusted so that the frequency is 50 kHz. The formula is

XTAL/FILTER_CLOCK_DIVIDE.

4.

The filter should be calibrated only when the crystal oscillator is settled. The filter calibration is initiated every time Bit R6_DB19 is set high.

5.