Preliminary Technical Data

ADF7020

Rev. PrH | Page 31 of 40

REGISTER 4—DEMODULATOR SETUP REGISTER

DEMODULATOR LOCK SETTING

POSTDEMODULATOR BW

ADDRESS

BITS

DS2

0

0

1

1

DS1

0

1

0

1

DEMODULATOR

TYPE

LINEAR DEMODULATOR

CORRELATOR/DEMODULATOR

ASK/OOK

INVALID

LM2

0

0

0

0

1

1

DEMOD MODE

0

1

2

3

4

5

LM1

0

0

1

1

0

1

DEMOD LOCK/SYNC WORD MATCH

SERIAL PORT CONTROL – FREE RUNNING

SERIAL PORT CONTROL – LOCK THRESHOLD

SYNC WORD DETECT – FREE RUNNING

SYNC WORD DETECT – LOCK THRESHOLD

INTERRUPT/LOCK PIN LOCKS THRESHOLD

DEMOD LOCKED AFTER DL8–DL1 BITS

INT/LOCK PIN

–

–

OUTPUT

OUTPUT

INPUT

–

DL8

0

1

0

1

X

DL8

DL7

0

0

0

.

1

1

DL8

0

0

0

.

1

1

DL3

0

0

0

.

1

1

...

...

...

...

...

...

...

DL2

0

0

1

.

1

1

DL1

0

1

0

.

0

1

LOCK_THRESHOLD_TIMEOUT

0

1

2

.

254

255

MODE5 ONLY

Figure 32.

Notes :

1.

The cutoff frequency of the postdemodulator filter should typically be 0.75 times the data rate.

2.

Demodulator modes 1, 3, 4, and 5 are modes that can be activated to allow the ADF7020 to demodulate data-encoding schemes that have run-length constraints

greater than 7.

3.

4.

For Mode 5, the timeout delay to lock threshold = (LOCK_THRESHOLD_SETTING)/SEQ_CLK, where SEQ_CLK is defined in the Register 3—Receiver Clock Register

section.