Preliminary Technical Data

ADF7020

Rev. PrH | Page 25 of 40

REGISTER 0—N REGISTER

TR1

TRANSMIT/

RECEIVE

0

TRANSMIT

RECEIVE

1

M3

M2

M1

MUXOUT

0

REGULATOR READY (DEFAULT)

0

R DIVIDER OUTPUT

0

N DIVIDER OUTPUT

0

DIGITAL LOCK DETECT

1

ANALOG LOCK DETECT

1

THREE-STATE

1

PLL TEST MODES

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

Σ-∆ TEST MODES

PLE1 PLL ENABLE

0

PLL OFF

1

PLL ON

N8

N7

N6

N5

N4

N3

N2

N1

N COUNTER

DIVIDE RATIO

031

032

.

.

.

1

253

1

254

1

0

0

.

.

.

1

1

1

0

1

.

.

.

.

.

.

1

1

1

1

0

1

1

1

.

.

.

1

0

1

1

1

.

.

.

1

0

1

1

1

.

.

.

1

0

0

1

1

.

.

.

.

.

.

1

0

1

0

1

255

15-BIT FRACTIONAL-N

8-BIT INTEGER-N

MUXOUT

ADDRESS

BITS

FRACTIONAL

DIVIDE RATIO

4

5

6

.

.

.

32764

32765

32766

32767

M15

0

0

0

.

.

.

1

1

1

1

M14

0

0

0

.

.

.

1

1

1

1

M13

0

0

0

.

.

.

1

1

1

1

...

...

...

...

...

...

...

...

...

...

...

M3

1

1

1

.

.

.

1

1

1

1

M2

0

0

1

.

.

.

0

0

1

1

M1

0

1

0

.

.

.

0

1

0

1

Figure 26.

Notes:

1.

The Tx/Rx bit (R0_DB27) configures the part in Tx or Rx mode and also controls the state of the internal Tx/Rx switch.

2.

)

2

(

15

-N

Fractional

Integer-N

R

XTAL

F

OUT

+

×

=

.