WM8993 datasheet(55/229 Pages) WOLFSON

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Production Data

WM8993

PD, November 2010, Rev 4.0

ANTI-CLIP CONTROL

The DRC includes an Anti-Clip feature to avoid signal clipping when the input amplitude rises very

quickly. This feature uses a feed-forward technique for early detection of a rising signal level. Signal

clipping is avoided by dynamically increasing the gain attack rate when required. The Anti-Clip

feature is enabled using the DRC_ANTICLIP_ENA bit.

Note that the feed-forward processing increases the latency in the input signal path. For low-latency

applications (e.g. telephony), it may be desirable to reduce the delay, although this will also reduce

the effectiveness of the anti-clip feature. The latency is determined by the DRC_FF_DELAY bit. If

necessary, the latency can be minimised by disabling the anti-clip feature altogether.

The DRC Anti-Clip control bits are described in Table 23.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R125 (7Dh)

DRC Control 3

DRC_FF_DELAY

Feed-forward delay for anti-clip

feature

0 = 5 samples

1 = 9 samples

Time delay can be calculated as

5/fs or 9/ fs, where fs is the sample

rate.

R123 (7Bh)

DRC Control 1

DRC_ANTICLIP_

ENA

Anti-clip enable

0 = disabled

1 = enabled

Table 23 DRC Anti-Clip Control

Note that the Anti-Clip feature operates entirely in the digital domain. It cannot be used to prevent

signal clipping in the analogue domain nor in the source signal. Analogue clipping can only be

prevented by reducing the analogue signal gain or by adjusting the source signal.

QUICK RELEASE CONTROL

The DRC includes a Quick-Release feature to handle short transient peaks that are not related to the

intended source signal. For example, in handheld microphone recording, transient signal peaks

sometimes occur due to user handling, key presses or accidental tapping against the microphone.

The Quick Release feature ensures that these transients do not cause the intended signal to be

masked by the longer time constants of DRC_DECAY_RATE.

The Quick-Release feature is enabled by setting the DRC_QR_ENA bit. When this bit is enabled, the

DRC measures the crest factor (peak to RMS ratio) of the input signal. A high crest factor is

indicative of a transient peak that may not be related to the intended source signal. If the crest factor

exceeds the level set by DRC_THRESH_QR, then the normal decay rate (DRC_DECAY_RATE) is

ignored and a faster decay rate (DRC_RATE_QR) is used instead.

The DRC Quick-Release control bits are described in Table 24.

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