WM8993 datasheet(85/229 Pages) WOLFSON

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Production Data

WM8993

PD, November 2010, Rev 4.0

CHARGE PUMP

The WM8993 incorporates a dual-mode Charge Pump which generates the supply rails for the

headphone output drivers, HPOUT1L and HPOUT1R.

The Charge Pump has a single supply input, CPVDD, and generates split rails CPVOUTP and

CPVOUTN according to the selected mode of operation.

The Charge Pump connections are illustrated in Figure 23 (see “Electrical Characteristics” for

external component values). An input decoupling capacitor may also be required at CPVDD,

depending upon the system configuration.

Figure 23 Charge Pump External Connections

The Charge Pump is enabled by setting the CP_ENA bit. When enabled, the charge pump adjusts

the output voltages (CPVOUTP and CPVOUTN) as well as the switching frequency in order to

optimise the power consumption according to the operating conditions. This can take two forms,

which are selected using the CP_DYN_PWR register bit.

•

Dynamic control (CP_DYN_PWR = 1)

Under Register control, the HPOUT1L_VOL and HPOUT1R_VOL register settings are used to

control the charge pump mode of operation.

Under Dynamic control, the audio signal level in the DAC is used to control the charge pump mode of

operation. This is the Wolfson ‘Class W’ mode, which allows the power consumption to be optimised

in real time, but can only be used if the DAC is the only signal source. This mode should not be used

if any of the bypass paths are used to feed analogue inputs into the output signal path.

Under the recommended usage conditions of the WM8993, the Charge Pump will be enabled by

running the default headphone Start-Up sequence as described in the “Control Write Sequencer”

section. (Similarly, it will be disabled by running the Shut-Down sequence.) In these cases, the user

does not need to write to the CP_ENA bit. The Charge Pump operating mode defaults to Register

control; Dynamic control may be selected by setting the CP_DYN_PWR register bit, if appropriate.

Note that the charge pump clock is derived from internal clock CLK_SYS; either MCLK or the FLL

output selectable using the SYSCLK_SRC bit. Under normal circumstances an external clock signal

must be present for the charge pump to function. However, the FLL has a free-running mode that

does not require an external clock but will generate an internal clock suitable for running the charge

pump. The clock division from CLK_SYS is handled transparently by the WM8993 without user

intervention, as long as CLKSYS and sample rates are set correctly. Refer to the “Clocking and

Sample Rates” section for more detail on the FLL and clocking configuration.

The Charge Pump control fields are described in Table 55.

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