WM8993 datasheet(151/229 Pages) WOLFSON

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Production Data

WM8993

PD, November 2010, Rev 4.0

151

WSEQ

INDEX

ADDRESS

WIDTH

START

DATA

DELAY

EOS

DESCRIPTION

56 (38h)

R56 (38h)

1 bit

Bit 7

00h

LINEOUT_VMID_BUF_ENA = 0

(delay = 0.5625ms)

57 (39h)

R55 (37h)

1 bit

Bit 0

00h

VROI = 0

(delay = 0.5625ms)

58 (3Ah)

R57 (39h)

6 bits

Bit 1

00h

BIAS_SRC = 0

STARTUP_BIAS_ENA = 0

VMID_BUF_ENA = 0

VMID_RAMP[1:0] = 00b

(delay = 0.5625ms)

Table 101 Generic Shut-Down Default Sequence

POP SUPPRESSION CONTROL

The WM8993 incorporates a number of features, including Wolfson’s SilentSwitch™ technology,

designed to suppress pops normally associated with Start-Up, Shut-Down or signal path control. To

achieve maximum benefit from these features, careful attention is required to the sequence and

timing of these controls. Note that, under the recommended usage conditions of the WM8993, these

features will be configured by running the default Start-Up and Shut-Down sequences as described in

the “Control Write Sequencer” section. In these cases, the user does not need to set these register

fields directly.

The Pop Suppression controls relating to the Headphone / Line Output drivers are described in the

“Output Signal Path” section.

Additional bias controls, also pre-programmed into Control Write Sequencer, are described in the

“Reference Voltages and Master Bias” section.

DISABLED LINE OUTPUT CONTROL

The line outputs are biased to VMID in normal operation. In order to avoid audible pops caused by a

disabled signal path dropping to AGND, the WM8993 can maintain these connections at VMID when

the relevant output stage is disabled. This is achieved by connecting a buffered VMID reference to

the output. The buffered VMID reference is enabled by setting VMID_BUF_ENA. The output

resistance can be either 1000

Ω or 20kΩ, depending on the VROI register bit.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R55 (37h)

Additional

Control

VROI

Buffered VMID to Analogue Line

Output Resistance (Disabled Outputs)

0 = 20k

Ω from buffered VMID to

output

1 = 1000

Ω from buffered VMID to

output

R57 (39h)

AntiPOP2

VMID_BUF_ENA

VMID Buffer Enable

0 = Disabled

1 = Enabled

Table 102 Disabled Line Output Control

LINE OUTPUT DISCHARGE CONTROL

The line output paths can be actively discharged to AGND through internal resistors if desired. This is

desirable at start-up in order to achieve a known output stage condition prior to enabling the soft-start

VMID reference voltage. This is also desirable in shut-down to prevent the external connections from

being affected by the internal circuits. The line outputs LINEOUT1P and LINEOUT1N are discharged

to AGND by setting LINEOUT1_DISCH. The line outputs LINEOUT2P and LINEOUT2N are

discharged to AGND by setting LINEOUT2_DISCH.

WM8993 Datasheet(PDF) 151 Page - Wolfson Microelectronics plc

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