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WM8993 Datasheet(PDF) 160 Page - Wolfson Microelectronics plc |
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WM8993 Datasheet(HTML) 160 Page - Wolfson Microelectronics plc |
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160 / 229 page  WM8993 Production Data w PD, November 2010, Rev 4.0 160 QUICK START-UP AND SHUTDOWN The default control sequences (see “Control Write Sequencer”) contain only the register writes necessary to enable or disable specific output drivers. It is therefore necessary to configure the signal path and gain settings before commanding any of the default start-up sequences. This section describes minimum control sequences to configure the WM8993 for DAC to Headphone playback. Note that these sequences are provided for guidance only; application software should be verified and tailored to ensure optimum performance. Table 110 describes an example control sequence to enable the direct DAC to Headphone path. This involves DAC enable, signal path configuration and mute control, together with the default “Headphone Cold Start-Up” sequence. Table 111 describes an example control sequence to disable the direct DAC to Headphone path. Note that these sequences are provided for guidance only; Application software should be verified and tailored to ensure optimum performance. REGISTER VALUE DESCRIPTION R3 (03h) 0003h Enable DACL and DACR R45 (2Dh) 0100h Enable path from DACL to HPOUT1L R46 (2Eh) 0100h Enable path from DACR to HPOUT1R R73 (49h) 0100h Initiate Control Write Sequencer at Index Address 0 (Headphone ‘cold’ Start-Up) Delay 300ms Note: Delay must inserted in the sequence to allow the Control Write Sequencer to finish. Any control interface writes to the CODEC will be ignored while the Control Write Sequencer is running. R10 (0Ah) 0000h Soft un-mute DAC Table 110 DAC to Headphone Direct Start-Up Sequence REGISTER VALUE DESCRIPTION R10 (0Ah) 0004h Soft mute DAC R73 (49h) 012Ah Initiate Control Write Sequencer at Index Address 42 (Generic Shut-Down) Delay 525ms Note: Delay must inserted in the sequence to allow the Control Write Sequencer to finish. Any control interface writes to the CODEC will be ignored while the Control Write Sequencer is running. R45 (2Dh) 0000h Disable path from DACL to HPOUT1L R46 (2Eh) 0000h Disable path from DACR to HPOUT1R R3 (03h) 0000h Disable DACL and DACR Table 111 DAC to Headphone Direct Shut-Down Sequence In both cases, the WSEQ_BUSY bit (in Register R74, see Table 93) will be set to 1 while the Control Write Sequence runs. When this bit returns to 0, the remaining steps of the sequence may be executed. Note that it is also possible to use GPIO or Interrupt functions to confirm the status of the Control Write Sequencer - see “General Purpose Input/Output”. |
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