DP83959 datasheet(11/38 Pages) NSC

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4.0

Pin Descriptions (Continued)

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4.6

Signal Name

Type

Pin #

Description

RA4

RA3

RA2

RA1

RA0

I/O

These pins also provide DP83955/6 compatible LED status: during display

update cycles these pins become outputs that provide port address and data

for LED display purposes. Pins RA[1:4] cycle values from 0h to 9h while RA0

provides Bad Polarity status for the 10BASE-T ports. See Section 5.13 for

more details. If the DP83955/6 compatible LEDs and register interface are not

being used, these pins should be left unconnected.

In Option mode (see DEF/OPT), the logic levels present on RA[4:0] at reset

(set by pull-up or pull-down resistors) are latched into the conﬁguration

registers. See section 5.12 for more information.

I/O

Data [3:0]: Bi-directional register data. /RD and /WR control the data

direction. With /RD low and /WR high, D[3:0] are outputs and with /RD high

and /WR low, D[3:0] are inputs. These pins also provide the DP83955/6

compatible status outputs for latching to LEDs. See Section 5.13 for more

details. If the DP83955/6 compatible LEDs and register interface are not being

used, these pins should be left unconnected.

In Option mode (see DEF/OPT), the logic levels present on D[3:0] at reset (set

by pull-up or pull-down resistors) are latched into the conﬁguration registers.

See Section 5.12 for more information.

/RD

Read Strobe: When strobed low, this input schedules a register read access

to the register addressed by the RA[4:0] pins. If the register interface is not

being used, this pin should be connected to VCC either directly or via a pull-up

resistor (

≈4.7 kΩ).

/WR

Write Strobe: When strobed low, this input schedules a register write access

to the register addressed by the RA[4:0] pins. If the register interface is not

being used, this pin should be connected to VCC either directly or via a pull-up

resistor (

≈4.7 kΩ).

/READY

Ready Handshake: The falling edge of this active low signal during a read

cycle indicates that data is stable and valid for sampling. In write cycles, the

falling edge of /READY denotes that the write data has been latched by the

LeRIC8. Therefore, data must have been available and stable for this

operation to be successful.

/STR

Display Update Strobe: When using the DP83955/6 compatible status LEDs,

this active low signal controls the latching of display data for network ports into

the external display latches. If not required, this pin should be left

unconnected.

DFS

Display Frozen Strobe: Asserted high when the display data for each packet

is frozen at the end of the repeater transmission of the packet until the start of

the next network event or for a maximum of 30ms (nominal value). This

ensures DP83955/6 compatible status LEDs are visible even for single

network events.

BUFEN

Buffer Enable: Used to control an external buffer (if required) for the data

bus, D[3:0]. Extermal buffer will be necessary in systems having a register

interface.

/MLOAD

142

Mode Load/Reset: TTL level reset input (not Schmitt) for external reset or

test purposes. If not required, this pin should be connected to VCC either

directly or via a pull-up resistor (

≈4.7 kΩ). On the rising (trailing) edge of

/MLOAD, the logic levels present on the D[3:0] and RA[4:0] inputs (set by

pull-up or pull-down resistors) are latched into the conﬁguration registers.

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