DP83959 datasheet(22/38 Pages) NSC

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6.0

LERIC8 Registers

6.1

The LERIC8's register address map is shown below. Since

the data path is only a nibble wide interface, each register

has two addresses, with the most signiﬁcant address bit

(RA4) used to select either the lower or upper nibble of the

thought of as having data bits D[7:0], so that for the lower nib-

ble bits D[3:0] are presented on D[3:0] respectively and for

the upper nibble, bits D[7:4] are presented on D[3:0] respec-

tively. Register descriptions in the following sections are giv-

en in the byte wide notation, D[7:0].

Address

RA[4:0]

(4 3210)

0 0000

1 0000

LERIC8 Status - Lower Nibble

LERIC8 Status - Upper Nibble

0 0001

1 0001

Port0 (AUI) Status/Conﬁg - Lower Nibble

Port0 (AUI) Status/Conﬁg - Upper Nibble

0 0010

1 0010

Port1 Status/Conﬁg - Lower Nibble

Port1 Status/Conﬁg - Upper Nibble

0 0011

1 0011

Port2 Status/Conﬁg - Lower Nibble

Port2 Status/Conﬁg - Upper Nibble

0 0100

1 0100

Port3 Status/Conﬁg - Lower Nibble

Port3 Status/Conﬁg - Upper Nibble

0 0101

1 0101

Port4 Status/Conﬁg - Lower Nibble

Port4 Status/Conﬁg - Upper Nibble

0 0110

1 0110

Port5 Status/Conﬁg - Lower Nibble

Port5 Status/Conﬁg - Upper Nibble

0 0111

1 0111

Port6 Status/Conﬁg - Lower Nibble

Port6 Status/Conﬁg - Upper Nibble

0 1000

1 1000

Port7 Status/Conﬁg - Lower Nibble

Port7 Status/Conﬁg - Upper Nibble

0 1001

1 1001

Port8 Status/Conﬁg - Lower Nibble

Port8 Status/Conﬁg - Upper Nibble

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