DP83959 datasheet(19/38 Pages) NSC

19 / 38 page

5.0

Functional Description (Continued)

www.national.com

5.13

MIN/MAX MODE LED INTERFACE

The LERIC8 supports the Min and Max LED modes of the

DP83955/6 LERIC devices. If these modes are not required

(for instance, if only the direct drive LED outputs are being

used), then no actions/connections are required. If Min or

Max mode is required, the relevant circuitry is simply added

to the data and address bus pins. The /STR pin is used to

latch data into external latches for display on the status

LEDs.

For Min mode, the LERIC8 operates identically to the

DP83955/6 devices. Table 4 shows the interface pin func-

tions for Min mode.

For Max mode, since the LERIC8 has more ports than the

DP83955/6, a slightly different latching scheme is required.

Figure 7 shows how Max mode functions for the LERIC8.

Data for latching (into external 74x259 addressable latches)

is presented on the D[0:3] and RA0 pins. Address informa-

tion is presented on the RA[1:4] pins. The address cycles

from 0h through 9h and then returns to 0h and repeats con-

tinuously.

5.14

AUI PORT 0

The DP83959 LERIC8 has a single AUI port that uses the

standard 3 differential pairs of signal connections. The AUI

receiver input pairs (RX0+/- and CD0+/-) require external

line termination (78

Ω balanced termination). The AUI trans-

mit output pairs utilize class A/B output drivers and do not

require any source termination resistors (as did the

DP83955/6).

The three AUI signal pairs (RX, TX, CD) require the use of

an isolation transformer (standard AUI 1:1 type) in order to

meet the fault condition requirements of IEEE 802.3. A typ-

ical AUI port connection is shown in Figure 8.

5.15

10BASE-T PORTS 1-8

The DP83959 will directly support up to 8 10BASE-T ports.

Figure 9 shows a typical 10BASE-T port connection.

Each of the 10BASE-T ports uses 4 signal pins on the

DP83959 package (two for transmit outputs and two for re-

ceive inputs) plus a shared power and ground. This minimal

conﬁguration is possible due to the 10BASE-T ﬁltering and

waveshaping being implemented internal to the device’s

transmit circuitry. The DP83959 still requires the use of re-

ceive ﬁltering and termination and transmit source imped-

ance matching resistors external to the device. Decoupling

capacitors may also be required from the center taps of the

transmit and receive isolation transformers.

On transmit, the 10BASE-T ports of the DP83959 requires

the use of 1:2 step-up transformers in order to generate the

correct transmit output drive voltage. Common mode

chokes may not be required to meet emissions standards if

the layout guidelines are followed.

On receive, the 10BASE-T ports of the DP83959 requires

the use of 1:1 transformers. Filtering may be required to re-

duce high frequency interference.

Table 3

Default/Optional Mode Configuration Parameter Selection

Function

Effect When

Bit = 0

Effect When

Bit = 1

Default

Value

Description

Not Used: Don't Care, can leave unconnected.

Reserved

Not

Permitted

Required

Reserved: Must be set to 1

EPOLSW

Not Selected

Selected

Enables polarity switching of the receive squelch on

detecting polarity reversal of the incoming data.

RA0

Reserved

Not

Permitted

Required

Reserved: Must be set to 1

RA1

/TXONLY

Selected

Not Selected

Allows the port partition state machines to restrict segment

reconnection only to when a good packet is transmitted on

the partitioned port.

RA2

/CCLIM

The IEEE802.3 10Mb/s Section 9 repeater partition

speciﬁcation requires a port to be partitioned after a certain

number of consecutive collisions. The LERIC8 has two

values available to allow users to customize the partitioning

algorithm to their environment.

RA3

MIN/MAX

Minimum

Mode

Maximum

Mode

The operation of the DP83955/6 LERIC compatible LED

display update mode is controlled by this bit.

RA4

Not Used: Don't Care, can leave unconnected.

DP83959 Datasheet(PDF) 19 Page - National Semiconductor (TI)

DP83959 Datasheet(HTML) 19 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

Datasheet Download

Link URL