TMS320DM641 datasheet(147/171 Pages) TI

147 / 171 page

Video Port

147

June 2003 − Revised August 2004

SPRS222C

Table 4−54. Video Port 0 and 1 (VP0 and VP1) Control Registers (Continued)

HEX ADDRESS RANGE

DESCRIPTION

ACRONYM

VP0

DESCRIPTION

ACRONYM

VP1

[DM641 ONLY]

01C4 024C

01C4 424C

VD_VSYNE2x

Video Display Field 2 Vertical Synchronization End Register

01C4 0250

01C4 4250

VD_RELOADx

Video Display Counter Reload Register

01C4 0254

01C4 4254

VD_DISPEVTx

Video Display Display Event Register

01C4 0258

01C4 4258

VD_CLIPx

Video Display Clipping Register

01C4 025C

01C4 425C

VD_DEFVALx

Video Display Default Display Value Register

01C4 0260

01C4 4260

VD_VINTx

Video Display Vertical Interrupt Register

01C4 0264

01C4 4264

VD_FBITx

Video Display Field Bit Register

01C4 0268

01C4 4268

VD_VBIT1x

Video Display Field 1Vertical Blanking Bit Register

01C4 026C

01C4 426C

VD_VBIT2x

Video Display Field 2Vertical Blanking Bit Register

7400 000

7800 0000

Y_RSCA

Y FIFO Source Register A

7400 0008

7800 0008

CB_SRCA

CB FIFO Source Register A

7400 0010

7800 0010

CR_SRCA

CR FIFO Source Register A

7400 0020

7800 0020

Y_DSTA

Y FIFO Destination Register A

7400 0028

7800 0028

CB_DST

CB FIFO Destination Register A

7400 0030

7800 0030

CR_DST

CR FIFO Destination Register A

TMS320DM641 Datasheet(PDF) 147 Page - Texas Instruments

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