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TMS320DM641 Datasheet(PDF) 151 Page - Texas Instruments

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Part # TMS320DM641
Description  Video/Imaging Fixed-Point Digital Signal Processors
PDF  171 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320DM641 Datasheet(HTML) 151 Page - Texas Instruments

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Video Port
151
June 2003 − Revised August 2004
SPRS222C
Table 4−59. Switching Characteristics Over Recommended Operating Conditions in Video
Display Mode for Video Data and Control Output Shown With Respect to
VPxCLKINx and VPxCLKOUTx†‡ (see Figure 4−51)
NO.
PARAMETER
−400
−500
−600
UNIT
MIN
MAX
1
tc(VKO)
Cycle time, VPxCLKOUTx
V − 0.7
V + 0.7
ns
2
tw(VKOH)
Pulse duration, VPxCLKOUTx high
VH − 0.7
VH + 0.7
ns
3
tw(VKOL)
Pulse duration, VPxCLKOUTx low
VL − 0.7
VL + 0.7
ns
4
tt(VKO)
Transition time, VPxCLKOUTx
1.8
ns
5
td(VKIH-VKOH)
Delay time, VPxCLKINx high to VPxCLKOUTx high§
1.1
5.7
ns
6
td(VKIL-VKOL)
Delay time, VPxCLKINx low to VPxCLKOUTx low§
1.1
5.7
ns
7
td(VKIH-VKOL)
Delay time, VPxCLKINx high to VPxCLKOUTx low
1.1
5.7
ns
8
td(VKIL-VKOH)
Delay time, VPxCLKINx low to VPxCLKOUTx high
1.1
5.7
ns
9
td(VKIH-VPOUTV) Delay time, VPxCLKINx high to VPxOUT valid¶
9
ns
10
td(VKIH-VPOUTIV) Delay time, VPxCLKINx high to VPxOUT invalid¶
1.7
ns
11
td(VKOH-VPOUTV) Delay time, VPxCLKOUTx high to VPxOUT valid†¶
4.3
ns
12
td(VKOH-VPOUTIV) Delay time, VPxCLKOUTx high to VPxOUT invalid†¶
−0.2
ns
† V = the video input clock (VPxCLKINx) period in ns.
‡ VH is the high period of V (video input clock period) in ns and VL is the low period of V (video input clock period) in ns.
§ Assuming non-inverted VPxCLKOUTx signal.
¶ VPxOUT consists of VPxCTLx and VPxD[7:0]
VPxCLKINx
VPxCLKOUTx
[VCLK2P = 0]
VPxCLKOUTx
(Inverted)
[VCLK2P = 1]
VPxCTLx,
VPxD[7:0]
(Outputs)
VPxCTLx
(Input)
5
7
1
3
2
6
8
9
13
10
14
11
12
15
16
4
4
Figure 4−51. Video Port Display Data Output Timing and Control Input/Output Timing
With Respect to VPxCLKINx and VPxCLKOUTx



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