TMS320DM641 datasheet(155/171 Pages) TI

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Ethernet Media Access Controller (EMAC)

155

June 2003 − Revised August 2004

SPRS222C

4.15

Ethernet Media Access Controller (EMAC)

The EMAC controls the flow of packet data from the DSP to the PHY.

4.15.1

EMAC Device-Specific Information

The ethernet media access controller (EMAC) provides an efficient interface between the DM641/DM640 DSP

core processor and the network. The DM641/DM640 EMAC support both 10Base-T and 100Base-TX, or 10

Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of

service (QOS) support. The DM641/DM640 EMAC makes use of a custom interface to the DSP core that

allows efficient data transmission and reception.

The EMAC controls the flow of packet data from the DSP to the PHY. The MDIO module controls PHY

configuration and status monitoring.

Both the EMAC and the MDIO modules interface to the DSP through a custom interface that allows efficient

data transmission and reception. This custom interface is referred to as the EMAC control module, and is

considered integral to the EMAC/MDIO peripheral. The control module is also used to control device reset,

interrupts, and system priority.

The TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO)

Module Reference Guide (literature number SPRU628) describes the DM641/DM640 EMAC peripheral in

detail. Some of the features documented in this peripheral reference guide are not supported on the

DM641/DM640 at this time. The DM641/DM640 supports one receive channel and does not support receive

quality of service (QOS). For a list of supported registers and register fields, see Table 4−63 [Ethernet MAC

(EMAC) Control Registers] and Table 4−64 [EMAC Statistics Registers] in this data manual.

4.15.2

EMAC Peripheral Register Description(s)

Table 4−63. Ethernet MAC (EMAC) Control Registers

HEX ADDRESS RANGE

ACRONYM

01C8 0000

TXIDVER

Transmit Identification and Version Register

01C8 0004

TXCONTROL

Transmit Control Register

01C8 0008

TXTEARDOWN

Transmit Teardown Register

01C8 000C

−

Reserved

01C8 0010

RXIDVER

Receive Identification and Version Register

01C8 0014

RXCONTROL

Receive Control Register

01C8 0018

RXTEARDOWN

Receive Teardown Register

(RXTDNCH field only supports writes of 0.)

01C8 001C − 01C8 00FF

−

Reserved

01C8 0100

RXMBPENABLE

Receive Multicast/Broadcast/Promiscuous Channel Enable Register

(The RXQOSEN field is reserved and only supports writes of 0. The

PROMCH, BROADCH, and MUCTCH bit fields only support writes of 0.)

01C8 0104

RXUNICASTSET

Receive Unicast Set Register

(Bits 7−1 are reserved and only support writes of 0.)

01C8 0108

RXUNICASTCLEAR

Receive Unicast Clear Register

(Bits 7−1 are reserved and only support writes of 0.)

01C8 010C

RXMAXLEN

Receive Maximum Length Register

01C8 0110

RXBUFFEROFFSET

Receive Buffer Offset Register

01C8 0114

RXFILTERLOWTHRESH

Receive Filter Low Priority Packets Threshold Register

01C8 0118 − 01C8 011F

−

Reserved

01C8 0120

RX0FLOWTHRESH

Receive Channel 0 Flow Control Threshold Register

TMS320DM641 Datasheet(PDF) 155 Page - Texas Instruments

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