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TMS320DM641 Datasheet(PDF) 154 Page - Texas Instruments |
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TMS320DM641 Datasheet(HTML) 154 Page - Texas Instruments |
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154 / 171 page ![]() VCXO Interpolated Control (VIC) 154 June 2003 − Revised August 2004 SPRS222C 4.14.3 VIC Electrical Data/Timing 4.14.3.1 STCLK Timing Table 4−62. Timing Requirments for STCLK† (see Figure 4−53) NO. −400 −500 −600 UNIT MIN MAX 1 tc(STCLK) Cycle time, STCLK 33.3 ns 2 tw(STCLKH) Pulse duration, STCLK high 16 ns 3 tw(STCLKL) Pulse duration, STCLK low 16 ns 4 tt(STCLK) Transition time, STCLK 3 ns † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. STCLK 2 3 1 4 4 Figure 4−53. STCLK Timing |
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