TMS320DM641 datasheet(150/171 Pages) TI

150 / 171 page

Video Port

150

June 2003 − Revised August 2004

SPRS222C

4.13.3.3 VCLKIN Timing (Video Display Mode)

Table 4−57. Timing Requirements for Video Display Mode for VPxCLKINx† (see Figure 4−50)

NO.

−400

−500

−600

UNIT

MIN

MAX

tc(VKI)

Cycle time, VPxCLKINx

tw(VKIH)

Pulse duration, VPxCLKINx high

4.1

tw(VKIL)

Pulse duration, VPxCLKINx low

4.1

tt(VKI)

Transition time, VPxCLKINx

† The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.

VPxCLKINx

Figure 4−50. Video Port Display VPxCLKINx Timing

4.13.3.4 Video Control Input/Output and Video Display Data Output Timing With Respect to

VPxCLKINx and VPxCLKOUTx (Video Display Mode)

Table 4−58. Timing Requirements in Video Display Mode for Video Control Input Shown With

Respect to VPxCLKINx and VPxCLKOUTx (see Figure 4−51)

NO.

−400

−500

−600

UNIT

MIN

MAX

tsu(VCTLV-VKIH)

Setup time, VPxCTLx valid before VPxCLKINx high

2.9

th(VCTLV-VKIH)

Hold time, VPxCTLx valid after VPxCLKINx high

0.5

tsu(VCTLV-VKOH) Setup time, VPxCTLx valid before VPxCLKOUTx high‡

7.4

th(VCTLV-VKOH)

Hold time, VPxCTLx valid after VPxCLKOUTx high‡

−0.9

‡ Assuming non-inverted VPxCLKOUTx signal.

TMS320DM641 Datasheet(PDF) 150 Page - Texas Instruments

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