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TMS570LS3137 Datasheet(PDF) 134 Page - Texas Instruments |
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TMS570LS3137 Datasheet(HTML) 134 Page - Texas Instruments |
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134 / 173 page ![]() TMS570LS3137 SPNS162C – APRIL 2012 – REVISED APRIL 2015 www.ti.com Table 7-17. FlexRay Jitter Timing PARAMETER MIN MAX UNIT tTx1bit Clock jitter and signal symmetry 98 102 ns tTx10bit FlexRay BSS (byte start sequence) to BSS 999 1001 ns tTx10bitAvg Average over 10,000 samples 999.5 1000.5 ns Delay difference between rise and fall from Rx pin to sample tRxAsymDelay – 2.5 ns point in FlexRay core tjit(SCLK) Jitter for the 80-MHz Sample Clock generated by the PLL – 0.5 ns 7.5.3 FlexRay Transfer Unit The FTU can transfer data between the input buffer (IBF) and output buffer (OBF) of the communication controller and the system memory without CPU interaction. Because the FlexRay module is accessed through the FTU, the FTU must be powered up by setting bit 23 in the Peripheral Power Down Registers of the System Module before accessing any FlexRay module register. For more information on the FTU, see the TMS570LS31x/TMS570LS21x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual (SPNU499). 134 Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback |
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