VT8231 datasheet(105/132 Pages) ETC

105 / 132 page

VT8231

Preliminary Revision 0.8 October 29, 1999

-99-

Power Management I/O-Space Registers

7HFKQRORJLHV ,QF

:H &RQQHFW

I/O Offset 3B-38 - GP Timer Reload Enable ..................RW

All bits in this register default to 0 on power up.

31-8 Reserved

..........................................always read 0

GP1 Timer Reload on KBC Access

Normal GP1 Timer Operation................default

Setting of KBC_STS causes the GP1 timer to

reload.

GP1 Timer Reload on Serial Port Access

Normal GP1 Timer Operation ...............default

Setting of COMA_STS or COMB_STS causes

the GP1 timer to reload.

Reserved

..........................................always read 0

GP1 Timer Reload on VGA Access

Normal GP1 Timer Operation ...............default

Setting of VGA_STS causes the GP1 timer to

reload.

GP1 Timer Reload on IDE/Floppy Access

Normal GP1 Timer Operation ...............default

Setting

FDC_STS,

SIDE_STS,

PIDE_STS causes the GP1 timer to reload.

GP3 Timer Reload on GPIO Range 1 Access

Normal GP3 Timer Operation ...............default

Setting of GR1_STS causes the GP3 timer to

reload.

GP2 Timer Reload on GPIO Range 0 Access

Normal GP2 Timer Operation ...............default

Setting of GR0_STS causes the GP2 timer to

reload.

GP0 Timer Reload on Primary Activity

Normal GP0 Timer Operation ...............default

Setting of PACT_STS causes the GP0 timer to

reload. Primary activities are enabled via the

Primary Activity Detect Enable register (offset

37-34) with status recorded in the Primary

Activity Detect Status register (offset 33-30).

I/O Offset 40 – Extended I/O Trap Status ................... RWC

7-2

Reserved

......................................... always read 0

GPIO Ramge 3 Access Status ............. (GPR3_STS)

GPIO Ramge 2 Access Status ............. (GPR2_STS)

I/O Offset 42 – Extended I/O Trap Enable..................... RW

7-2

Reserved

......................................... always read 0

SMI on GPIO Ramge 3 Access.............(GPR3_EN)

Disable................................................... default

1Enable

SMI on GPIO Ramge 2 Access.............(GPR2_EN)

Disable................................................... default

1Enable

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