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Soft-Start and Powergood

80%

87%

100%

85

µs

45

µs

UDG−04066

T

2

C

VDDQ

V

VDDQ

0.8

I

VDDQOCP

) 85 ms

(2)

T

C

VTT

V

VTT

I

VTTOCL

(3)

VDDQ and VTT Discharge Control

TPS51116

SLUS609A – MAY 2004 – REVISED JUNE 2004

DETAILED DESCRIPTION (continued)

The soft start function of the SMPS is achieved by ramping up reference voltage and two-stage current clamp. At

the starting point, the reference voltage is set to 650 mV (87% of its target value) and the overcurrent threshold

is set half of the nominal value. When UVP comparator detects VDDQ become greater than 80% of the target,

the reference voltage is raised toward 750 mV using internal 4-bit DAC. This takes approximately 85 µs. The

overcurrent threshold is released to nominal value at the end of this period. The powergood signal waits another

45 µs after the reference voltage reaches 750 mV and the VDDQ voltage becomes good (above 95% of the

target voltage), then turns off powergood open-drain MOSFET.

The soft-start function of the VTT LDO is achieved by current clamp. The current limit threshold is also changed

in two stages using an internal powergood signal dedicated for LDO. During VTT is below the powergood

threshold, the current limit level is cut into 60% (2.2 A).This allows the output capacitors to be charged with low

and constant current that gives linear ramp up of the output. When the output comes up to the good state, the

overcurrent limit level is released to normal value (3.8 A). TPS51116 has an independent counter for each

output, but the PGOOD signal indicates only the status of VDDQ and does not indicate VTT powergood

externally. See Figure 1.

Figure 1. VDDQ Soft-Start and Powergood Timing

assumed. Note that both switchers and the LDO do not start up with full load condition.

TPS51116 discharges VDDQ, VTTREF and VTT outputs during S3 and S5 are both low. There are two different

discharge modes. The discharge mode can be set by connecting MODE pin as shown in Table 3.

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