www.ti.com

R

p

f

0

V

OUT

0.75

C

O

gm

R

S

(18)

R

V

OUT

C

R

(19)

1

C

O

ESR

1

C

C2

R

C

(20)

C

C

O

ESR

R

C

(21)

f

1

2p

C

C

R

C

+

f

0

10

(22)

R1 +

V

0.75

R2

(23)

D-CAP™ Mode Operation

TPS51116

SLUS609A – MAY 2004 – REVISED JUNE 2004

APPLICATION INFORMATION (continued)

5. Calculate C

of ceramic capacitor(s) is used, no need for C

6. Calculate C

causes phase delay, another zero to cancel this effect at f

by Cc and Rc. Recommended

ωz1 is 10 times lower to the f

7. When using adjustable mode, determine the value of R1 and R2. Recommended R2 value is from 100

k

Ω to 300 kΩ. Determine R1 using Equation 23.

A buck converter system using D-CAP™ Mode can be simplified as below.

Figure 3. Linearizing the Modulator

The VDDQSNS voltage is compare with internal reference voltage after divider resistors. The PWM comparator

determines the timing to turn on top MOSFET. The gain and speed of the comparator is high enough to keep the

voltage at the beginning of each on cycle (or the end of off cycle) substantially constant. The DC output voltage

may have line regulation due to ripple amplitude that slightly increases as the input voltage increase.

16