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Current Protection for VDDQ

V

10 (mA)

(4)

I

V

TRIP

R

DS(on)

)

I

RIPPLE

2

+

V

TRIP

R

DS(on)

)

1

2

L

f

V

V

OUT

V

IN

(5)

Current Protection for VTT

Overvoltage and Undervoltage Protection for VDDQ

TPS51116

SLUS609A – MAY 2004 – REVISED JUNE 2004

DETAILED DESCRIPTION (continued)

Table 3. Discharge Selection

MODE

DISCHARGE MODE

V5IN

No discharge

VDDQ

Tracking discharge

S4/GND

Non-tracking discharge

When in tracking-discharge mode, TPS51116 discharges outputs through the internal VTT regulator transistors

and VTT output tracks half of VDDQ voltage during this discharge. Note that VDDQ discharge current flows via

VLDOIN to LDOGND thus VLDOIN must be connected to VDDQ output in this mode. The internal LDO can

handle up to 3 A and discharge quickly. After VDDQ is discharged down to 0.2 V, the internal LDO is turned off

and the operation mode is changed to the non-tracking-discharge mode.

When in non-tracking-discharge mode, TPS51116 discharges outputs using internal MOSFETs which are

connected to VDDQSNS and VTT. The current capability of these MOSFETs are limited to discharge slowly.

Note that VDDQ discharge current flows from VDDQSNS to PGND in this mode. In case of non-tracking mode,

TPS51116 does not discharge output charge at all.

The SMPS has cycle-by-cycle over current limiting control. The inductor current is monitored during the OFF

state and the controller keeps the OFF state during the inductor current is larger than the over current trip level.

The trip level and current sense scheme are determined by CS pin connection (see Current Sensing Scheme

resistor.

In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output

the output voltage tends to be even lower. Eventually, it crosses the undervoltage protection threshold and

shutdown.

The LDO has an internally fixed constant over current limiting of 3.8 A while operating at normal condition. This

trip point is reduced to 2.2 A before the output voltage comes within

±5% of the target voltage or goes outside of

±10% of the target voltage.

TPS51116 monitors a resistor divided feedback voltage to detect overvoltage and undervoltage. If VDDQSET is

connected to V5IN or GND, the feedback voltage is made by an internal resistor divider inside VDDQSNS pin. If

an external resistor divider is connected to VDDQSET pin, the feedback voltage is VDDQSET voltage itself.

When the feedback voltage becomes higher than 115% of the target voltage, the OVP comparator output goes

high and the circuit latches as the top MOSFET driver OFF and the bottom MOSFET driver ON.

Also, TPS51116 monitors VDDQSNS voltage directly and if it becomes greater than 4 V TPS51116 turns off the

top MOSFET driver. When the feedback voltage becomes lower than 70% of the target voltage, the UVP

comparator output goes high and an internal UVP delay counter begins counting. After 32 cycles, TPS51116

latches OFF both top and bottom MOSFETs. This function is enabled after 1007 cycles of SMPS operation to

ensure startup.

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