TUSB3200A datasheet(46/102 Pages) TI1

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TUSB3200A

SLES018B – OCTOBER 2001 – REVISED FEBRUARY 2011

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2.2.15.1 Port 3 GPIO Bits

As illustrated in Figure 2-8, alternative inputs on port 3 are routed directly from the DI input at the MCU

core interface to their destination within the MCU core. It is also noted that when the port bit is used as an

alternative input, the value of the input can still be read by the MCU. If the port bit is to be used as a

general-purpose input, the firmware must make the proper settings so that the alternative logic unit that

receives the general-purpose input does not erroneously respond to the input.

Each alternative output on port 3 is ANDed with the memory-mapped latch (Special Function Register

−

SFR) assigned to that port bit, and the result is DO. This means that if the alternate output is to be used,

the latch must be set to logic 1. Similarly, if the latch is to be the source for DO, the alternate output must

be logic 1. (The MCU core assures that if the logical unit supplying the alternate output is not used, its

default state is logic 1).

Power-up initialization of P3.0 and P3.1 results in indeterminate output state (that is, three-state, pulldown,

or pullup) until the MCU clock begins operating, at which time the pins are high-impedance, until the

application program effects a change.

2.2.15.1.1 UART Alternative Functions

Port 3 GPIO bits P3.0 and P3.1, in addition to being able to serve as general-purpose I/O bits, can also

serve to implement UART functionality. The UART implemented offers four modes of operation. In mode

0, UART output data is output on port bit P3.0 and the transmit clock (MCU clock/12) is output on port bit

P3.1. In modes 1, 2, and 3, UART receive data is input on P3.0 and UART transmit data is output on

P3.1. Modes 1, 2, and 3 are then full duplex modes; serial data can be transmitted and received

simultaneously.

In all four UART modes, transmission is initiated by any instruction that accesses the MCU-core register

SBUF. If this register is not written to, the alternate output lines for P3.0 and P3.1 are at their default logic

1 state. P3.0 and P3.1 can then be used as general-purpose outputs if no instructions access register

SBUF.

The REN bit in the MCU serial port control register SCON enables UART reception if set to logic 1. If REN

is cleared to logic 0, using P3.0 as a general-purpose input does not result in erroneous behavior in the

UART logic block. P3.1 has no alternative input function, and thus it can be used as a general-purpose

input if the latch assigned to that bit is set to logic 1 and no instructions access register SBUF. (P3.0 also

requires that its latch be set to logic 1 and that no instructions access register SBUF if it is to be used as a

general-purpose input).

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