TUSB3200A datasheet(79/102 Pages) TI1

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TUSB3200A

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SLES018B – OCTOBER 2001 – REVISED FEBRUARY 2011

A.5.2.12 DMA Channel 0 Control Register (DMACTL0

− Address FFE8h)

The DMA channel 0 control register is contains various control bits for DMA channel 0.

BIT

MNEMONIC

DMAEN

WABEN

—

EPDIR

EPNUM2

EPNUM1

EPNUM0

TYPE

R/W

DEFAULT

BIT

MNEMONIC

NAME

DESCRIPTION

DMAEN

DMA enable

The DMA enable bit is set to a 1 by the MCU to enable this DMA channel. Before

enabling the DMA channel, all other DMA channel configuration bits should be set to

the desired value.

WABEN

The wrap-around buffer enable bit is used by the MCU to enable or disable the

wrap-around buffer operation. The wrap-around buffer operation can only be used by

isochronous out endpoints or isochronous in endpoints that are serviced by the DMA

channels. The wrap-around buffer operation is enabled or disabled separately for

each DMA channel. For a DMA channel, the MCU should set this bit to a 1 to enable

the wrap-around buffer operation and clear this bit to a 0 to disable the wrap-around

buffer operation. Both the DMA channel and UBM logic use this bit to determine the

required functionality.

—

Reserved

Reserved for future use

—

Reserved

Reserved for future use

EPDIR

USB endpoint direction

The USB endpoint direction bit controls the direction of data transfer by this DMA

channel. The MCU should set this bit to a 1 to configure this DMA channel to be used

for a USB in endpoint. The MCU should clear this bit to a 0 to configure this DMA

channel to be used for a USB out endpoint.

2:0

EPNUM(2:0)

USB endpoint number

The USB endpoint number bits are set by the MCU to define the USB endpoint

number supported by this DMA channel. Keep in mind that endpoint 0 is always used

for the control endpoint, which is serviced by the MCU and not a DMA channel.

001b = Endpoint 1,

010b = Endpoint 2, …,

111b = Endpoint 7

MCU Memory and Memory-Mapped Registers

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