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TUSB3200A Datasheet(PDF) 85 Page - Texas Instruments

Part # TUSB3200A
Description  USB Streaming Controller (STC)
PDF  102 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TUSB3200A Datasheet(HTML) 85 Page - Texas Instruments

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TUSB3200A
www.ti.com
SLES018B – OCTOBER 2001 – REVISED FEBRUARY 2011
A.5.4.3
Codec Port Interface Configuration Register 3 (CPTCNF3
− Address FFDEh)
The codec port interface configuration register 3 is used to store various control bits for the codec port
interface operation.
BIT
7
6
5
4
3
2
1
0
MNEMONIC
DDLY
TRSEN
CSCLKP
CSYNCP
CSYNCL
BYOR
CSCLKD
CSYNCD
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DEFAULT
0
0
1
1
0
0
0
0
BIT
MNEMONIC
NAME
DESCRIPTION
7
DDLY
Data delay
The data delay bit is set to a 1 by the MCU to program a one CSCLK cycle delay of
the serial data output and input signals in reference to the leading edge of the
CSYNC signal. The MCU should clear this bit to a 0 for no delay between these
signals.
6
TRSEN
3-State enable
The 3-state enable bit is set to a 1 by the MCU to program the hardware to 3-state
the serial data output signal for the time slots during the audio frame that are not
valid. The MCU should clear this bit to a 0 to program the hardware to use
zero-padding for the serial data output signal for time slots during the audio frame
that are not valid.
5
CSCLKP
CSCLK polarity
The CSCLK polarity bit is used by the MCU to program the clock edge used for the
codec port interface frame sync (CSYNC) output signal, codec port interface serial
data output (CDATO) signal and codec port interface serial data Input (CDATI)
signal. When this bit is set to a 1, the CSYNC signal will be generated with the
negative edge of the codec port interface serial clock (CSCLK) signal. Also, when
this bit is set to a 1, the CDATO signal will be generated with the negative edge of
the CSCLK signal and the CDATI signal will be sampled with the positive edge of
the CSCLK signal. When this bit is cleared to a 0, the CSYNC signal will be
generated with the positive edge of the CSCLK signal. Also, when this bit is cleared
to a 0, the CDATO signal will be generated with the positive edge of the CSCLK
signal and the CDATI signal will be sampled with the negative edge of the CSCLK
signal.
4
CSYNCP
CSYNC polarity
The CSYNC polarity bit is set to a 1 by the MCU to program the polarity of the
codec port interface frame sync (CSYNC) output signal to be active high. The MCU
should clear this bit to a 0 to program the polarity of the CSYNC output signal to be
active low.
3
CSYNCL
CSYNC length
The CSYNC length bit is set to a 1 by the MCU to program the length of the codec
port interface frame sync (CSYNC) output signal to be the same number of CSCLK
cycles as time slot 0. The MCU should clear this bit to a 0 to program the length of
the CSYNC output signal to be one CSCLK cycle.
2
BYOR
Byte order
The byte order bit is used by the MCU to program the byte order for the data moved
by the DMA between the USB endpoint buffer and the codec port interface. When
this bit is set to a 1, the byte order of each audio sample will be reversed when the
data is moved to/from the USB endpoint buffer. When this bit is cleared to a 0, the
byte order of the each audio sample will be unchanged.
This bit is ineffective for MONO I2S channels.
1
CSCLKD
CSCLK direction
The CSCLK direction bit is set to a 1 by the MCU to program the direction of the
codec port interface serial clock (CSCLK) signal as an input to the TUSB3200A
device. The MCU should clear this bit to a 0 to program the direction of the CSCLK
signal as an output from the TUSB3200A device.
0
CSYNCD
CSYNC direction
The CSYNC direction bit is set to a 1 by the MCU to program the direction of the
codec port interface frame sync (CSYNC) signal as an input to the TUSB3200A
device. The MCU should clear this bit to a 0 to program the direction of the CSYNC
signal as an output from the TUSB3200A device.
Copyright © 2001–2011, Texas Instruments Incorporated
MCU Memory and Memory-Mapped Registers
85
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