LE25S161 datasheet(8/54 Pages) ONSEMI

8 / 54 page

LE25S161

www.onsemi.com

5. Pin Description

Symbol

Pin Name

Description

Chip select

The device becomes active when the logic level of this pin is low; it is deselected and placed in

standby status when the logic level of the pin is high.

SCK

Serial clock

This pin controls the data input/output timing.

The input data and addresses are latched synchronized to the rising edge of the serial clock, and

the data is output synchronized to the falling edge of the serial clock.

(SIO0)

Serial data input

(Serial data input output)

I/O

The data and addresses are input from this pin, and latched internally synchronized to the rising

edge of the serial clock.

(It changes into input/output pin during the Dual operation.)

(SIO1)

Serial data output

(Serial data input output)

I/O

The data stored inside the device is output from this pin synchronized to the falling edge of the

serial clock.

( It changes into input/output pin during the Dual operation.)

Write protect

The Write Status Register Protect (SRWP) takes effect when the logic level of this pin is low.

HOLD

Hold

Serial communication is suspended when the logic level of this pin is low.

VDD

Power supply

This pin supplies the 1.65 to 1.95V supply voltage.

VSS

Ground

This pin supplies the 0V supply voltage.

LE25S161 Datasheet(PDF) 8 Page - ON Semiconductor