LE25S161 datasheet(22/54 Pages) ONSEMI

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LE25S161

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10-6. Dual read

There are two Dual read commands, the Dual Output Read (RDDO) and the Dual I/O Read (RDIO).

They achieve the twice speed-up from "High-Speed Read (RDHS: 0Bh)". The command list is shown in "Table.1-2.

Command Settings (Dual SPI)"

Pin Configurations at Dual SPI Mode

Standard SPI

Dual SPI



SIO0



SIO1

10-6-1. Dual Output Read command (RDDO)

Maximum Clock frequency: 50MHz

The SI and SO pins change into the input/output pin (SIOx) during this operation. It makes the data output x2 bit and has

achieved a high-speed output. bit7, 5, 3 and bit1are output from SIO0. bit6, 4, 2 and bit0 are output from SIO1.

"Figure 8. Dual Output Read (RDDO)" shows the timing waveforms.

The sequence of RDDO operation :

CS goes to low  input RDDO command (3Bh)  3 Byte address (A23-A0) input on SI

 1 byte dummy cycle  the corresponding data out on SI/SIO0 and SO/SIO1

 continuous data out (n-byte) per 4clock 

 completed by CS=high

* The data output starts from the falling edge of SCK(39th clock)

Output Data

SI/SIO0

bit6,4,2,0

SO/SIO1

bit7,5,3,1

The Address is latched on rising edge of SCK. It is necessary to add 1 dummy byte cycle after address is latched, and the

corresponding data is shifted out on SI/SIO0 and SO/SIO1 by the falling edge of SCK. The address is automatically

incremented to the next higher address after each byte data (4 clock cycles) is shifted out. If the SCK input is continued

after the internal address arrives at the highest address (1FFFFFh), the internal address returns to the lowest address

(000000h). By setting CS to high, the device is deselected, and the read cycle is completed. While the device is deselected,

the output pin SO is in a high-impedance state.

Figure 8. Dual Output Read (RDDO)

● Address A23 to A21 are "Don't care".

DATA0: bit6,bit4,bit2,bit0

DATA1: bit7,bit5,bit3,bit1

Add

(A7-A0)

Add

(A15-A8)

Add

(A23-A16)

High Impedance

DATA1

SCK

SIO1

SIO0

3Bh

MSB

31 32

39 40

43 44

Mode3

Mode0

8CLK

MSB

Byte 3

Byte 2

Byte 1

DATA0

4CLK

dummy

bit

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